參數(shù)資料
型號(hào)： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 97/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240I
Lucent Technologies Inc.
Lucent Technologies Inc.
97
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Timing Characteristics
(continued)
Table 37. OR3TP12 FPGA Side Interface Clock to Output Delays, pciclk Synchronous Signals
OR3TP12 Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C < T
A
< 70 °C.
Note: The clock to out parameters are measured from the
pciclk
clock output pin on the FPGA side, excluding the interbufs, which traverse
the ASIC/FPGA boundary. The ORCA Foundry static analysis tool, trace, accounts for clock skew and interbuf delays on the clock
and data paths.
Table 38. OR3TP12 FPGA Side Interface Clock to Output Delays, fclk Synchronous Signals
OR3TP12 Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C < T
A
< 70 °C.
Note: The clock to out parameters are measured from the
fclk1
and
fclk2
clock input pins on the FPGA side, excluding the interbufs, which
traverse the ASIC/FPGA boundary. The ORCA Foundry static analysis tool, trace, accounts for clock skew and interbuf delays on
the clock and data paths.
Description
(T
I
= 85 °C, V
DD
= min, V
DD
2 = min)
tcmd[3:0]
bar[2:0]
pci_cfg_stat
Min
Max
Unit
—
—
—
5.124
4.586
11.383
ns
ns
ns
Description
(TI = 85 °C, V
DD
= min, V
DD
2 = min)
fpga_msyserror
ma_fulln
mstatecntr[3:0]
m_ready
mw_fulln
mw_afulln
datatofpga[31:0]
(dual-port mode)
datatofpgax[3:0]
(dual-port mode)
mrdata[17:0]
(quad-port mode)
twdata[17:0]
(quad-port mode)
mr_emptyn
mr_aemptyn
mrlastcycn
disctimerexpn
treqn
t_ready
tstatecntr[3:0]
tw_emptyn
tw_aemptyn
twlastcycn
tr_fulln
tr_afulln
trlastcycn
Min
Max
Unit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.468
4.230
5.049
4.996
4.918
4.056
12.514
11.347
12.514
11.229
4.302
4.169
8.835
3.673
5.643
4.779
5.716
4.741
4.360
10.212
4.554
4.216
6.154
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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