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| 型號： | OR3TP12-6PS240I |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 103/128頁 |
| 文件大?。?/td> | 2450K |
| 代理商： | OR3TP12-6PS240I |
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Lucent Technologies Inc.
Lucent Technologies Inc.
103
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Table 41. FPGA Common-Function Pin Descriptions
(continued)
** The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Symbol
I/O
Description
Special-Purpose Pins
(continued)
TDI, TCK, TMS
I
I/O
O
If boundary scan is used, these pins are test data in, test clock, and test mode select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited
once configuration is complete. Even if boundary scan is not used, either TCK or
TMS must be held at logic one during configuration. Each pin has a pull-up enabled
during configuration.
After configuration, these pins are user-programmable I/O.*
During configuration in peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the
same status is also available on D7 in asynchronous peripheral mode.
During the Master parallel configuration mode, RCLK is a read output signal to an
external memory. This output is not normally used.
In i960microprocessor mode, this pin acts as the address latch enable (ALE) input.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
High during configuration is output high until configuration is complete. It is used as
a control output indicating that configuration is not complete.
Low during configuration is output low until configuration is complete. It is used as a
control output indicating that configuration is not complete.
INIT is a bidirectional signal before and during configuration. During configuration, a
pull-up is enabled, but an external pull-up resistor is recommended. As an active-low
open-drain output, INIT is held low during power stabilization and internal clearing of
memory. As an active-low input, INIT holds the FPGA in the wait-state before the
start of configuration.
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and micropro-
cessor configuration modes. The FPGA is selected when CS0 is low and CS1 is
high. During configuration, a pull-up is enabled.
RDY/RCLK/
MPI_ALE
O
I
I/O
O
HDC
LDC
O
INIT
I/O
CS0, CS1
I
I/O
I
After configuration, these pins are user-programmable I/O pins.*
RD is used in the asynchronous peripheral configuration mode. A low on RD
changes D7 into a status output. As a status indication, a high indicates ready, and a
low indicates busy. WR and RD should not be used simultaneously. If they are, the
write strobe overrides.
This pin is also used as the microprocessor interface (MPI) data transfer strobe. For
PowerPC it is the transfer start (TS). For i960, it is the address/data strobe (
ads
).
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
WR is used in the asynchronous peripheral configuration mode. When the FPGA is
selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an
internal data buffer. WR and RD should not be used simultaneously. If they are, the
write strobe overrides.
After configuration, this pin is a user-programmable I/O pin.*
RD/MPI_STRB
I
I/O
I
WR
I/O
Pin Information
(continued)
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