參數(shù)資料
型號： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 78/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240I
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
78
L Lucent Technologies Inc.
PCI Bus Core Target Controller Detailed Description
(continued)
The read data phase will follow, by deassertion of
taenn
, assertion of Target read data enable (
trdataenn
).
trda-
taenn
can only be asserted while
tr_fulln
is deasserted, indicated that space is available in the read data FIFOs.
While
trdataenn
is asserted, the FPGA application will transfer Target read data on bus
datafmfpga
to the read
data FIFOs. The FPGA application is informed when the last component of the data phase is need when
trlast-
cycn
is asserted. In a burst access, this is during the last data phase. Assuming this is a burst access, (
datatofp-
gax[1]
= 1 during command/address phase),
trlastcycn
is deasserted during the read data phase except for the
last data of the read data phase. After receiving
trlastcycn
at the end of the data phase,
trdataenn
must be deas-
serted by the FPGA application.
trlastcycn
can only be asserted when
trdataenn
is asserted. See Read Data
Transfer section for details on
trlastcycn
.
For quad-port mode (Figure 32), the address data is transferred on the bus
twdata
in 16-bit segments. The
address will be split into two 16-bits components with the LSB being transferred first. A burst operation and dual-
address indication accompanies the address on
twdata[17]
and
twdata[16]
respectively. Assuming a BAR size
greater than 16 bits, the address phase will require two clock cycles for a 32-bit address, and
twlastcycn
will be
asserted on the final or MSB component of the address. The data phase will also require two clock cycles to trans-
fer every 32-bit read data word across the 16-bit bus
trdata
from the FPGA application.
trlastcycn
will be deas-
serted for all 16-bit components of the read data phase, except for the final 16-bit component where it is asserted.
5-7550(F)
Figure 33. Target Memory Burst Read, Nondelayed (PCI Bus, 32-Bit)
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
Tn4
ADDRESS
D0
D1
D2
D3
MEM RD
BE0
BE0
BE1
BE2
BE3
clk
framen
ad
c_ben
irdyn
devseln
trdyn
stopn
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OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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