參數(shù)資料
型號(hào)： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 39/128頁
文件大小： 2450K
代理商： OR3TP12-6PS240I
Lucent Technologies Inc.
Lucent Technologies Inc.
39
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller Detailed Description
(continued)
Example: Master Write, Single-Word Transaction
Figure 3 and Figure 4 shows the timing of a Master write, single 32-bit data word, on the dual-port FPGA interface
and quad-port FPGA interface, respectively. In Figure 3, the command/address phase is initiated by the FPGA
application asserting Master address enable (
maenn
), while providing the Master command word on bus
datafmf-
pga
. On the next clock, the FPGA application provides the 32-bit address and ends the command/address phase
by asserting
mwlastcycn
for the write data phase.
To enter the data phase,
maenn
is deasserted,
mwdataenn
is asserted, and a valid 32-bit Dword of data provided
on bus
datafmfpga
. For a 32-bit transfer on a 32-bit PCI bus (
pci_64bit
= 0), the FPGA application asserts the sig-
nal
mwlastcycn
during the only clock of the data phase. After the first write data word is provided,
ma_fulln
goes
active indicating the Master will be begin negotiating for the PCI bus.
For quad-port mode (Figure 4), the command/address and write data is transferred on the bus
mwdata
in 16-bit
segments. The 18-bit Master command will remain unchanged, but the 32-bit address will be split into two 16-bit
components with the LSB being transferred first. The command/address phase will require three clock cycles
(
maenn
asserted), and
mwlastcycn
will be asserted on the final or MSB component of the address.
The data phase will also require additional clock cycles to transfer the 32-bit write data word across the bus
mwdata
. Similar to above, the data phase will be entered with the deassertion of
maenn
and assertion of
mwda-
taenn
.
mwlastcycn
will be deasserted for the initial 16-bit LSB of the write data word and asserted for the final
16-bit MSB component.
In Figure 5, execution begins on the PCI bus which shows the timing of a transaction with an external Target. The
transaction results in a normal completion. It is a typical PCI transaction with a remote Target that supports fast
decode, and the protocol and timing are as required by the PCI Specification.
5-7350(F)
Figure 3. Master Write Single (FIFO Interface, Dual-Port)
T0
T1
T2
T3
T4
T5
0
1
A
0
CMD
ADRS
D0
fclk
m_ready
mstatecntr
ma_fulln
datafmfpga
maenn
mw_fulln
mwdataenn
mwlastcycn
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