參數(shù)資料
型號(hào)： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 13/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240I
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Lucent Technologies Inc.
Lucent Technologies Inc.
13
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
The following sections describe the operation of the embedded PCI bus core interface.
PCI Bus Commands
The PCI bus core supports all commands required by the PCI Specification. The following table describes each
command. Subsequent sections will describe the protocols in which the commands are used.
Table 3. PCI Bus Command Descriptions
Command
Code
(Binary)
0000
Command
OR3TP12
Master
Generates
—
OR3TP12
Target
Accepts
—
Description
Interrupt
Acknowledge
Only implemented by Master agents that interface to the
system CPU and as Target by agents that incorporate the
system interrupt controller.
Target ignores, per PCI Specification Section 3.7.2.
Target
: Single accesses only, with bursts disconnected
after first data phase.
Delayed Mode (
deltrn
= 0): Terminates the initial access
with a retry, recording internally the PCI address and byte
enables for processing by the FPGA application. Subse-
quent PCI accesses occurring before the FPGA application
loads the Target read FIFO continues to result in retries.
After the Target read FIFO is loaded by the FPGA applica-
tion, the next read access that matches the stored parame-
ters disconnects with the FPGA supplied data and the
Target read logic is cleared.
Nondelayed Mode (
deltrn
= 1,
trburstpendn
= 0):
Accepted access inserts wait-states up to the initial latency
count (16 or 32 clocks depending on the option selected in
the FPSC configuration manager). During the wait-states,
the FPGA application processes the read request and
transfers data into the Target read FIFOs. If read data is
transferred into the Target read FIFOs before the latency
count expires, this read data is transferred to the PCI bus
during initial request. If not, the PCI address, byte enables,
and Target read data remain stored in the Target controller.
The next access that matches the stored address and byte
enables disconnects with the FPGA supplied data, and the
Target read logic is cleared.
Master:
Single and burst operations are allowed.
0001
0010
Special Cycle
I/O Read
—
√
—
√
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