參數(shù)資料
型號： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 44/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240I
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
44
L Lucent Technologies Inc.
PCI Bus Core Master Controller
Detailed Description
(continued)
The Master uses the read burst count supplied during
command/address phase to determine number of
64-bit words the Master read operation should transfer
(unlike the Master write, which uses signal
mwlast-
cycn
). If the burst length for a Master read operation is
the same as for the previous Master operation, the
FPGA application may elect to set bit 17 of the Master
command word. In this case, no burst length is sup-
plied; and the read burst length from the previous oper-
ation is used. This saves a clock cycle during the
command/address phase when in quad-port mode, but
should remain zero for the dual-port mode.
All read transactions require an address on a 64-bit
boundary, which requires
ad2
= 0. The read burst
length will indicate the number 64-bit words to retrieve
from this address. All burst read transaction may trans-
fer twice the read burst length of 32-bit words on a
32-bit PCI bus (
pci_64bit
= 0). On a 64-bit PCI bus
(
pci_64bit
= 1), the number of transfers may equal the
read burst length. All read byte enables in the Master
command word must be asserted for a burst read
transaction.
Single 32-bit transactions require a burst length of one.
For single 32-bit reads on a 32-bit PCI bus
(
pci_64bit
= 0), the read byte enables MRDBEN[7:0]
can modify the start address. Using MRDBEN[7:0] =
xf0 will not modify the start address, whereas MRD-
BEN[7:0] = x0f will. For example on a 32-bit data bus
(
pci_64bit
= 0), a read transaction with an even 64-bit
starting address and read byte enables of 0x0f will
retrieve a 32-bit word at the starting address + 0x4. For
the case of read byte enables of 0xf0, the 32-bit word
will be retrieved from the starting address.
Read Data Phase Transfer
The FPGA application begins the read data phase by
deasserting
maenn
and asserting
mrdataenn
. On
every cycle that
mrdataenn
is asserted and
fifo_sel
is
deasserted, the FPGA application will receive read
data from the Master read FIFO (sixty-four 32-bit
words; thirty-two 64-bit words) via bus
mrdata
(quad-
port mode) or
datatofpga
(dual-port mode), providing
the read data FIFOs are not empty (
mr_emptyn
= 1).
No byte enables are collected from the PCI bus, and
therefore
mrdata[17:16]
and
datatofpgax[3:0]
will be
unused.
mrdataenn
must not be asserted when the
read data FIFOs are empty (
mr_emptyn
is asserted).
Note that
mr_emptyn
can be updated on the same
clock edge as
mrdataenn
is sampled.
The distinction between a burst read and a single
access is provided by the read burst length count and
the Master read byte enables. When the read burst is
greater than one, or has all of its read byte enables
asserted with
pci_64bit
= 0, it informs the Master of a
burst read data phase for 32-bit PCI buses. During
bursts,
mrlastcycn
will be deasserted for every data
element received from the Master FIFO interface while
mrdataenn
is asserted (
fifo_sel
is deasserted), except
the last element. For a single 32-bit word transfer in
dual-port mode on a 32-bit PCI bus (
pci_64bit
= 0),
mrlastcycn
would be asserted during the entire data
phase, since the last data phase is the only data phase
of this transfer. Note that for
mrlastcycn
to be
asserted,
mrdataenn
must be asserted.
When executing a burst Master read, or with 64-bit
agents (
pci_64bit
= 1), the read data transferred to the
FPGA application is always aligned on 64-bit address
boundaries, which may require transfer of extra read
data for activity on 32-bit PCI buses. For read transfers
from an odd 32-bit PCI address (
ad2
= 1), this will
imply receiving an extra 32-bit read data word from the
PCI bus at the beginning of the read data phase. For
transfers starting at an even PCI address (
ad2
= 0)
requiring an odd number of 32-bit data words, an extra
32-bit read data word is received at the end. The extra
read data can be discarded by the FPGA application.
For single 32-bit transactions, on 32-bit buses
(
pci_64bit
= 0), the Master FIFO interface will perform
the proper data alignment. The FPGA application only
needs to transfer the valid 32-bit word during the data
phase.
Master Read Data FIFO Empty/Almost Empty
When the Master read data FIFO contains four or fewer
64-bit data elements, the Master FIFO interface asserts
mr_aemptyn
, the almost empty indicator. This allows
some latency to exist in the FPGA’s response without
risking overreading the FIFO. When all locations in the
Master read data FIFO are empty, the Master FIFO
interface asserts
mr_emptyn
, the FIFO empty indica-
tor. Since data can be simultaneously written to and
read from the Master read FIFO, both
mr_aemptyn
and
mr_emptyn
can change states in either direction
multiple times in the course of a burst data transfer.
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