參數(shù)資料
型號： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 3/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240I
Lucent Technologies Inc.
3
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
List of Figures
Figures
Page
Figures
Page
Figure 1. OR3TP12 Array.......................................11
Figure 2. ORCA OR3TP12 PCI FPSC
Block Diagram .....................................................12
Figure 3. Master Write Single
(FIFO Interface, Dual-Port)..................................39
Figure 4. Master Write Single
(FIFO Interface, Quad-Port).................................40
Figure 5. Master Write Single
(PCI Bus, 32-Bit)..................................................40
Figure 6. Master Write Burst
(FIFO Interface, Dual-Port)..................................41
Figure 7. Master Write Burst
(FIFO Interface, Quad-Port).................................42
Figure 8. Master Write Burst
(PCI Bus, 32-Bit)..................................................42
Figure 9. Master Read Single
(FIFO Interface, Dual-Port)..................................46
Figure 10. Master Read Single
(FIFO Interface, Quad-Port).................................47
Figure 11. Master Read Single
(PCI Bus, 32-Bit)..................................................47
Figure 12. Master Read Burst
(FIFO Interface, Dual-Port)..................................49
Figure 13. Master Read Burst
(FIFO Interface, Quad-Port).................................50
Figure 14. Master Read Burst
(PCI Bus, 32-Bit)..................................................51
Figure 15. Target Configuration Write
(PCI Bus, 32-Bit)..................................................57
Figure 16. Target I/O Write, Nondelayed
(PCI Bus, 32-Bit)..................................................58
Figure 17. Target Memory Single Write
(PCI Bus, 32-Bit)..................................................59
Figure 18. Target Write Single
(FIFO Interface, Dual-Port)..................................60
Figure 19. Target Write Single
(FIFO Interface, Quad-Port).................................61
Figure 20. Target Memory Write Burst
(PCI Bus, 32-Bit)..................................................62
Figure 21. Target Write Burst
(FIFO Interface, Dual-Port)..................................63
Figure 22. Target Write Burst
(FIFO Interface, Quad-Port)...................................64
Figure 23. Target Configuration Read
(PCI Bus, 32-Bit)....................................................68
Figure 24. Target I/O Read, Delayed
(PCI Bus, 32-Bit)....................................................69
Figure 25. Target I/O Read, Nondelayed
(PCI Bus, 32-Bit)....................................................70
Figure 26. Target Single Memory Read,
Delayed (PCI Bus, 32-Bit)......................................71
Figure 27. Target Read Single
(FIFO Interface, Dual-Port) ....................................72
Figure 28. Target Read Single
(FIFO Interface, Quad-Port)...................................73
Figure 29. Target Memory Read Single,
Nondelayed Transaction (PCI Bus, 32-Bit).............74
Figure 30. Target Burst Memory Read,
Delayed (PCI Bus, 32-Bit)......................................75
Figure 31. Target Read Burst
(FIFO Interface, Dual-Port) ....................................76
Figure 32. Target Read Burst
(FIFO Interface, Quad-Port)...................................77
Figure 33. Target Memory Burst Read,
Nondelayed (PCI Bus, 32-Bit)................................78
Figure 34. FPSC Block Diagram and
Clock Network........................................................81
Figure 35. Serial Configuration Data Format—
Autoincrement Mode..............................................89
Figure 36. Serial Configuration Data Format—
Explicit Mode .........................................................89
Figure 37. ac Test Loads ..........................................99
Figure 38. Output Buffer Delays...............................99
Figure 39. Input Buffer Delays..................................99
Figure 40. Sinklim (T
J
= 25 °C, V
DD
= 3.3 V)..........100
Figure 41. Slewlim (T
J
= 25 °C, V
DD
= 3.3 V).........100
Figure 42. Fast (T
J
= 25 °C, V
DD
= 3.3 V) ..............100
Figure 43. Sinklim (T
J
= 125 °C, V
DD
= 3.0 V)........100
Figure 44. Slewlim (T
J
= 125 °C, V
DD
= 3.0 V).......100
Figure 45. Fast (T
J
= 125 °C, V
DD
= 3.0 V) ............100
Figure 46. Package Parasitics................................121
相關(guān)PDF資料
PDF描述
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
OR62 OR62 is a 6-input OR gate with 2x drive strength
OR73 7-input OR gate with 3x drive strength.
OR8GU41 DIFFUSED TYPE (HIGH SPEED RECTIFIER APPLICATIONS)
ORCAORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP127BA256-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP127BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR-401045290 制造商:ORTRONICS 功能描述:ORTRONICS 24 PORT MODULAR PATCH PANEL
OR40300011 制造商:ORTRONICS 功能描述:WORSTATION
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*