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| 型號： | OR3TP12-6PS240I |
| 英文描述： | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 65/128頁 |
| 文件大小： | 2450K |
| 代理商： | OR3TP12-6PS240I |
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Lucent Technologies Inc.
Lucent Technologies Inc.
65
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed Description
(continued)
Table 21. Quad-Port Target Write
1. When
treqn
is deasserted high, the Target interface is idle.
2. When
taenn
is asserted low, a command/address phase is in progress.
3.
taenn
must be asserted low for command/address data to transfer and state to change.
4.
taenn
must be deasserted high and
twdataenn
must be asserted low to execute the data phase.
5. Next state = 0 if
twlastcycn
is asserted low (end of Target write data).
6. Next state = 4 if
twlastcycn
is asserted low (end of Target command/address phase).
Target Read Operation
A Target read operation presents unique demands on the FPGA application because only in this operation does
the Target request data that is needed to complete the transaction after the PCI transaction has already begun on
the PCI bus. Target latency rules require that the data be acquired quickly or that the Target terminate the transac-
tion with a retry/disconnect. Also, once the transfer process is underway, the Target usually does not know how
much more data will be requested. The Target must prefetch data so that it will be available if needed.
Delayed Transactions
A signal (
deltrn
) from the FPGA application influences the behavior of Target read and I/O write operations. When
deltrn
is asserted-low, the Target controller logic will enter delayed mode on incoming Target reads (memory
or I/O) and I/O writes. Delayed mode will issue a retry to the external Master, but store internally the PCI address,
command, and write data (if an I/O write). The retry frees up the PCI bus for other activity, while the FPGA applica-
tion processes the Target request. When the external Master attempts the same transaction again to the Target,
read data will be transferred if the Target read FIFOs are nonempty. When this signal is inactive-high, the Target
controller will generate wait-states, until either the FIFO becomes not empty and transmits the read data, or until
the maximum initial latency value (16 or 32 clock cycles in the FPSC configuration manager) has been reached. If
deltrn
is deasserted,
twburstpendn
must be asserted.
This signal should be inactive when minimum initial latency is desired on the initial data word, at the expense of
overall PCI bus efficiency. Signal
deltrn
affects the transaction’s behavior on the initial data word, whereas signal
trburstpendn
affects subsequent data latency when the Target read data FIFO empties. When
trburstpendn
is
inactive, a disconnect without data results from an attempt to read from an empty read data FIFO, after data has
been transferring on the PCI bus. With
trburstpendn
active, the Target will wait for data from the FIFO by inserting
wait-states (up to the maximum subsequent latency value of eight, at which time a disconnect without data will be
generated). Asserting
trburstpendn
will minimize latency for this transaction’s data at the expense of overall PCI
bus efficiency.
trburstpendn
must remain static throughout a Target read transaction.
tstatecntr
Next State or
tstatecntr
0
1 or 4
Description
Data on Bus
twdata[17:0]
XX
2
, XXXX
16
Burst, Dual-Address,
PCIAddress[15:0]
Burst, Dual-Address,
PCIAddress[31:16]
Burst, Dual-Address,
PCIAddress[47:32]
Burst, Dual-Address,
PCIAddress[63:48]
BEN[1:0], PCIData[15:0]
BEN[3:2], PCIData[31:16]
BEN[5:4], PCIData[47:32]
BEN[7:6], PCIData[63:48]
Notes
0
0
Idle
1
Address[15:0]
2, 3, 6
1
2 or 4
Address[31:16]
2, 3, 6
2
3 or 4
Address[47:32]
2, 3, 6
3
4
Address[63:48]
2, 3, 6
4
5
6
7
5
Data[15:0]
Data[31:16]
Data[47:32]
Data[63:48]
4
6 or 0
7
4 or 0
4, 5
4
4, 5
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