參數(shù)資料
型號(hào)： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 41/128頁(yè)
文件大小： 2450K
代理商： OR3TP12-6PS240I
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Lucent Technologies Inc.
Lucent Technologies Inc.
41
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller Detailed Description
(continued)
Example: Master Write, Burst Transaction
Figure 6 and Figure 7 show the timing of a Master write of four 32-bit data words, on the dual-port FPGA interface
and quad-port FPGA interface, respectively. In Figure 6, the command/address phase is initiated by the FPGA
application asserting Master address enable (
maenn
), while providing the Master command word on bus
datafmf-
pga
. On the next clock, the FPGA application provides the 32-bit address and ends the command/address phase
by asserting
mwlastcycn
.
To enter the data phase,
maenn
is deasserted,
mwdataenn
is asserted, and a valid 32-bit Dword of data provided
on bus
datafmfpga
. After the second write data word is provided,
ma_fulln
goes active indicating the Master will
be begin negotiating for the PCI bus (assuming
mwpcihold
is deaserted). The FPGA application continues to sup-
ply data (three 32-bit Dwords) on bus
datafmfpga
with
mwdataenn
asserted, while monitoring the
mw_fulln
flag.
To indicate the completion of the data phase,
mwlastcycn
is asserted, along with
mwdataenn
, during the final
data word.
For quad-port mode (Figure 7), the command/address and write data is transferred on the bus
mwdata
. The 18-bit
Master command will remain unchanged, but the 32-bit address will be split into two 16-bit components with the
LSB being transferred first. The command/address phase will require three clock cycles (with
maenn
asserted),
and
mwlastcycn
will be asserted on the final or MSB component of the address.
The quad-port data phase will also require additional clock cycles to transfer the four 32-bit write data word across
the bus
mwdata
. Similar to above, the data phase will be entered with the deassertion of
maenn
and assertion of
mwdataenn
.
mwlastcycn
will be deasserted for all write data words, except being asserted for the final 16-bit
MSB component.
Execution begins on the PCI bus, as shown in Figure 8, which shows the timing with an external Target. The trans-
action runs to normal completion. It is a typical PCI transaction (the remote Target supports fast decode), and the
protocol and timing are as required by the PCI Specification.
5-7351(F)
Figure 6. Master Write Burst (FIFO Interface, Dual-Port)
T0
T1
T2
T3
T4
T5
T6
T7
T8
0
1
A
B
A
B
0
CMD
ADRS
D0
D1
D2
D3
fclk
m_ready
mstatecntr
ma_fulln
datafmfpga
maenn
mw_fulln
mwdataenn
mwlastcycn
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