參數(shù)資料
型號(hào)： OR3TP12-6PS240I
英文描述： Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 25/128頁(yè)
文件大小： 2450K
代理商： OR3TP12-6PS240I
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Lucent Technologies Inc.
Lucent Technologies Inc.
25
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Target FIFO Address and Command Register Control Signals
treqn
I
Target Request from PCI.
The Target asserts
treqn
as an indication to the
FPGA application that a PCI Target operation has been decoded and is pend-
ing.
treqn
signal will continue to be active until all data has been transferred
between the FPGA application and the Target FIFO interface. The FPGA appli-
cation should use
treqn
to qualify valid data on following buses:
tcmd
,
bar
,
twdata
(quad-port mode), and
datatofpga/datatofpgax
(dual-port mode)
taenn
O
Target Address Output Enable.
This active-low signal enables the PCI start
address to be transferred from the Target address FIFO to the FPGA applica-
tion, on either bus
twdata
(quad-port mode) or
datatofpga
(dual-port mode,
fifo_sel
= 1).
treqn
will be asserted to indicate a valid PCI Target address
exists.
tcmd[3:0]
I
Target Command Code.
This bus provides the PCI command code for a
pending Target operation, and is valid when
treqn
is asserted active-low.
bar[2:0]
I
Base Address Register Number
. This bus indicates which of the six BARs
decoded the PCI address for the current Target operation, and is valid when
treqn
is active-low. For 64-bit addresses, the BARs pairs will be indicated by
numbers 0, 2, and 4.
Target Write Data FIFO Signals
twdataenn
O
Target Write FIFO Data Enable.
This active-low signal enables data from the
Target write data FIFO onto bus
twdata
(quad-port mode) or
datatofpga
(dual-
port mode,
fifo_sel
= 1).
twdataenn
should not be asserted whenever the Tar-
get write data FIFO is empty (
tw_emptyn
= 0).
twdata[17:0]
(quad-port mode)
or
datatofpgax[3:0]
,
datatofpga[31:0]
(dual-port mode)
Address:
Dual-Address Indication:
Burst Indication:
Unused:
b. Target Write Data: Write data from PCI bus.
Data:
Write Enables:
tw_aemptyn
I
Target Write FIFO Almost Empty.
This active-low signal indicates that only
four more 64-bit data locations are available to be read from the Target write
data FIFO.
tw_emptyn
I
Target Write FIFO Empty.
This active-low signal indicates that the Target write
FIFO is empty.
twdataenn
should never be asserted if
tw_emptyn
is asserted.
fclk
*
fclk
*
—
—
fclk
*
I
Depending on the OR3TP12 configuration, only one of these buses will be
available to the FPGA application. For Target operations, these buses will carry
the same information, but in different sizes and bit lanes as summarized below:
Quad-Port Mode
a. Target Start Address: 32- or 64-bit PCI start address.
twdata[15:0]
twdata[16]
twdata[17]
Dual-Port Mode (
fifo_sel
= 1)
datatofpga[31:0]
datatofpgax[0]
datatofpgax[1]
datatofpgax[3:2]
twdata[15:0]
twdata[17:16]
datatofpga[31:0]
datatofpgax[3:0]
fclk
*
fclk
*
fclk
*
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
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