參數(shù)資料
型號(hào): MT8LLN22NCNE
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA316
封裝: 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù): 71/145頁
文件大小: 2285K
代理商: MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
31
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Core Interrupt Control (Device 7h, Function 0h)
5:2
Serial IRQ Frame Size. These bits select the frame size used by the Serial
IRQ logic. Valid values are:
0100: Frame size of 21 (17+4).
All other values reserved.
R/W
0
1:0
Start Frame Pulse Width. These bits define the Start Frame pulse width
generated by the Serial Interrupt control logic measured in PCI clocks.
Valid values are:
00: 4 Clocks
01: 6 Clocks
10: 8 Clocks
All other values are reserved.
R/W
0
ADDRESS: 65h
SYMBOL: CORE_INT
BITS
DESCRIPTION
PROPERTIES
RESET
7Reserved
R/W
0
6
H_IGNNE# disable. When set H_IGNNE# will be ignored. When clear,
H_IGNNE# will be treated normally.
R/W
0
5
H_IGNNE# invert. When set, the polarity of H_IGNNE# will be treated as
active high. When clear, H_IGGNE# will be treated as active low.
R/W
0
4
H_FERR# invert. When set, the polarity of H_FERR# will be treated as
active high. When clear, H_FERR# will be treated as active low.
R/W
0
3
IDE IRQ15 Enable. When set, IDE_SEC_IRQ will be routed to IRQ15. When
clear, IRQ15 is available for other uses.
R/W
0
2
IDE IRQ14 Enable. When set, IDE_PRI_IRQ will be routed to IRQ14. When
clear, IRQ14 is available for other uses.
R/W
0
1
Legacy Mouse Interrupt Enable from USB. When set, USB mouse inter-
rupts are enabled. When clear, USB mouse interrupts are disabled.
R/W
0
Legacy Keyboard Interrupt Enable from USB. When set, USB keyboard
interrupts are enabled. When clear, USB keyboard interrupts are
disabled.
R/W
0
Serial Interrupt Control (Device 7h, Function 0h) (continued)
ADDRESS: 64h
SYMBOL: SER_IRQ
BITS
DESCRIPTION
PROPERTIES
RESET
SCI Interrupt Routing (Device 7h, Function 0h)
ADDRESS: 66h
SYMBOL: SCI_INT_ROUT
BITS
DESCRIPTION
PROPERTIES
RESET
7
Interrupt Routing Disable. When set, interrupt routing of SCI interrupts
are disabled. When clear, SCI interrupts will be routed to one of the
interrupts shown below.
R/W
1
6:4
Reserved.
R/W
0
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