參數資料
型號: MT8LLN22NCNE
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA316
封裝: 27 X 27 MM, PLASTIC, BGA-316
文件頁數: 130/145頁
文件大?。?/td> 2285K
代理商: MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
85
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
Register A
INDEX: 0Ah
SYMBOL: RTC_REGA
BITS
DESCRIPTION
PROPERTIES
RESET
7
Update in Progress. When set, the update is in progress. When clear, the
update cycle will not start for at least 492 uS and the time, calendar, and
alarm information is available.
R/O
N/A
6:4
Divide Chain Select. Controls the divide chain for the oscillator.
000: Normal Operation.
R/W
N/A
3:0
Rate Select. Selects one of the 13 taps of the 15-stage divider.
0000: Periodic interrupt does not toggle.
0001: 3.90625 ms
0010: 7.8125 ms
0011: 122.070 s
0100: 244.141 s
0101: 488.281 s
0110: 976.5625 s
0111: 1.953125 ms
1000: 3.90625 ms
1001: 7.8125 ms
1010: 15.625 ms
1011: 31.25 ms
1100: 62.5 ms
1101: 125 ms
1110: 250 ms
1111: 500 ms
R/W
N/A
Register B
INDEX: 0Bh
SYMBOL: RTC_REGB
BITS
DESCRIPTION
PROPERTIES
RESET
7
Inhibit Update Cycles. When set, the time and calendar registers may be
safely updated. The current update cycle is aborted, and will not resume
until this bit is clear. When clear, the update cycle occurs
normally.
R/W
N/A
6
Enable Periodic Interrupts. When set, allows an interrupt to occur as
determined by the Rate Select bits of register A.
R/W
0
5
Alarm Interrupt Enable. When set, allows an interrupt to occur when an
alarm match sets the Alarm Flag during the update cycle. When clear,
interrupt is disabled. Interrupts may be programmed to occur once a sec-
ond, hour, day or month.
R/W
N/A
4
Update Ended Interrupt Enable. When set, allows an interrupt when the
update cycle ends. When clear, interrupt is disabled.
R/W
0
3
Square Wave. This bit serves no function, but is included for software
compatibility.
R/W
0
2
Data Mode. When set, date is represented in binary mode. When clear,
data is represented in BCD.
R/W
N/A
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