參數資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數： 144/145頁
文件大小： 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
98
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
5
APM_STS. APM Status. Set when a write occurred to the APM B2h regis-
ter causing generation of an SMI#. When set with APMC_EN set an SMI
will be signaled to the processor through the EOSMI flag, provided
SMI_EN is set.
R/WOTC
0
4
DEV_STS. Device Status. When set, indicates that one of the status bits in
DEVSTS (ACPI register 30h) is set. This bit is be cleared by resetting all bits
in the DEVSTS register. When set with DEV_EN set an SMI will be signaled
to the processor through the EOSMI flag, provided SMI_EN is set.
R/O
0
3
SOFTWARE_STS - Minute software timer for SMI generation. Will set
once per minute. When set with MINUTE_EN set an SMI will be signaled
to the processor through the EOSMI flag, provided SMI_EN is set.
R/WOTC
0
2
MA_STS. Master Abort Status. When set, a SMI# was generated due to I/
O Controller PCI cycle being Master Aborted.
R/WOTC
0
1
MILLI-SECOND_STS -64 millisecond timer for SMI generation. Will set
once per every 64 milliseconds. When set with MILLISECOND_EN set an
SMI will be signaled to the processor through the EOSMI flag, provided
SMI_EN is set.
R/WOTC
0
BIOS_STS. BIOS Status. When set, a write of one occurred to GBL_RLS bit.
When set with BIOS_EN set an SMI will be signaled to the processor
through the EOSMI flag, provided SMI_EN is set.
R/WOTC
0
Global Enable Register
ADDRESS: ACPI_BASE + 22h
SYMBOL: GLBEN
BITS
DESCRIPTION
PROPERTIES
RESET
15:12
Reserved.
R.W
0
11
IRQ_RSM_EN. IRQ Resume Enable. When set, enable corresponding sta-
tus bit in GLBLSTS to generate an SMI# event. When clear, disable SMI#
event.
R/W
0
10
EXT_SMI_EN. External SMI Enable. When set, enable corresponding sta-
tus bit in GLBLSTS to generate an SMI# event. When clear, disable SMI#
event.
R/W
0
9
LEGACY_USB_EN. Legacy USB Enable. When set, enable corresponding
status bit in GLBLSTS to generate an SMI# event. When clear, disable
SMI# event.
R/W
0
8
SECOND_EN. Secondary Status Enable. When set, enable corresponding
status bit in GLBLSTS to generate an SMI# event. When clear, disable
SMI# event.
R/W
0
7
GPE0_EN. GP Status 0 Enable. When set, enable corresponding status bit
in GLBLSTS to generate an SMI# event. When clear, disable SMI# event.
R/W
0000b
6
PM1_EN. PM1 Enable. When set, enable corresponding status bit in
GLBLSTS to generate an SMI# event. When clear, disable SMI# event.
R/W
0000b
Global Status Register (continued)
ADDRESS: ACPI_BASE + 20h
SYMBOL: GLBSTS
BITS
DESCRIPTION
PROPERTIES
RESET
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