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參數(shù)資料
| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 27/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
122
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
FUNCTIONAL DESCRIPTION
PCI Bus
Transactions on the PCI bus may either be initiated
by the I/O controller as a PCI bus master, or accepted
by the I/O controller as a PCI bus target.
I/O Controller Initiated PCI Transaction
Types
Table 21 identifies each of the potential transaction
types initiated by the I/O controller and executed on
the PCI bus. The I/O controller does not perform any
transaction type not listed in Table 21 when operating
as a bus master.
PCI Initiated Transaction Types
Table 22 identifies each of the potential transaction
types initiated on the PCI bus and accepted by the I/O
controller, as well as the actions performed in
response to each of these transaction types. The I/O
controller does not perform any transaction type not
listed in.
Table 21
I/O Controller to PCI Transaction Types
TRANSACTION TYPE
ACTION
MEMORY READ
Bus mastering READs initiated by IDE, USB, and LPC.
MEMORY READ LINE
Bus mastering READs initiated by IDE, USB, and LPC.
MEMORY WRITE
Bus mastering WRITEs initiated by IDE, USB, and LPC.
MEMORY WRITE AND INVALIDATE
Bus mastering WRITEs initiated by IDE, USB, and LPC.
Table 22
PCI Initiated Transaction Types
TRANSACTION TYPE
ACTION
INTERRUPT ACKNOWLEDGE
Issued by the Host to PCI bridge only.
SPECIAL CYCLE
Issued by the Host to PCI bridge only. Accepted cycles include
SHUTDOWN, HALT, and STOP CLOCK ACKNOWLEDGE.
I/O READ
I/O READ cycles may be either positively or subtractively
decoded. I/O reads not directed to an internal device are for-
warded to the LPC bus.
I/O WRITE
I/O WRITE cycles may be either positively or subtractively
decoded. I/O WRITEs not directed to an internal device are for-
warded to the LPC bus.
MEMORY READ
MEMORY READs may be treated as PCI delayed reads to free
up the PCI bus for other activities. MEMORY READs not
directed to an internal device are forwarded to the LPC bus.
MEMORY WRITE
MEMORY WRITEs directed to the I/O controller may be posted.
MEMORY WRITEs not directed to an internal device are for-
warded to the LPC bus.
MEMORY READ MULTIPLE
Treated the same as MEMORY READ cycle.
MEMORY READ LINE
Treated the same as MEMORY READ cycle.
CONFIGURATION READ
Type-0 configuration cycles supported.
CONFIGURATION WRITE
Type-0 configuration cycles supported.
MEMORY WRITE AND INVALIDATE
Treated the same as MEMORY WRITE cycle.
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