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| 型號(hào)： | MT8LLN22NCNE |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA316 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-316 |
| 文件頁(yè)數(shù)： | 39/145頁(yè) |
| 文件大?。?/td> | 2285K |
| 代理商： | MT8LLN22NCNE |
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Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
133
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
General Purpose I/O
Up to 41 General Purpose I/O (GPIO) are provided
by the I/O Controller. There are 16 GPIO dedicated to
the standby plane, 16 GPIO dedicated to the 3.3V
plane, and 9 GPIO that are shared with other signals.
GPIO may be programmed as inputs that may gener-
ate SMI or SCI events. Events may be edge or level trig-
gered. GPIO may also be programmed as outputs.
IDE Controller
The I/O Controller integrates two independent IDE
channels capable of supporting up to four hard drives,
CD-ROMs or ATAPI devices. The IDE controller sup-
ports Programmed I/O (PIO), ATA/33, ATA/66, and
ATA/100 data transfer modes for both primary and
secondary devices. Each device can be independently
programmed. In PIO mode the IDE interface can
transfer data up to 14 MB/s. and in bus master IDE
mode data is transferred up to 100 MB/s. The IDE
interface contains cache line FIFO depth per channel
for write/read cycles optimizing performance.
USB Controller
The I/O Controller integrates a PCI-based imple-
mentation of the Universal Serial Bus (USB) 1.0 Speci-
fication utilizing the OpenHCI standard. The USB
interface contains two integrated Root Hubs with four
USB ports, and USB Host Controller. Keyboard and
Mouse legacy support are also included for DOS com-
patibility with USB devices.
SMB Controller
SMB Host Controller
The SMB Host controller allows the processor to
issue commands to other SMB slave devices. The host
controller supports seven SMB interface command
protocols for communicating with SMBus slave: Quick
Command, Send Byte, Receive Byte, Write Byte/Word,
Read Byte/Word, Process Call, and Block Read/Write.
Reference System Management Bus Specification revi-
sion 1.1 for the precise usage of these commands.
Commands are initiated by setting up a data structure
in the I/O space defined by SMB_BASE consisting of
command, address, byte count (where applicable),
data, and transfer type. The transfer will begin when
the processor sets the transfer start bit in the SMB Pro-
tocol register.
SMB Slave Interface
The SMB slave interface will allow an external SMB
controller to access the PCI configuration registers
integrated in the I/O Controller, as well as other inter-
nal status. The SMB Slave interface accepts only Read
Byte or Write Byte protocols, as defined by the SMB
bus specification. The main restriction of the Read
Byte and Write Byte protocols are that the addressable
spaces are limited to 256-bytes. A separate convention
is used to allow addressing of multiple 256-byte
addressable spaces. This interface is 8-bit addressable
and does not support packet error checking.
The I/O Controller employs multiple 256-byte con-
figuration records. When the number of addressable
registers exceeds 256-bytes, which is the limit of a sin-
C6h
1Fh
DMA Channel 5 Current Count High Byte.
C8h
20h
DMA Channel 6 Current Address Low Byte.
C8h
21h
DMA Channel 6 Current Address High Byte.
CAh
22h
DMA Channel 6 Current Count Low Byte.
CAh
23h
DMA Channel 6 Current Count High Byte.
CCh
24h
DMA Channel 7 Current Address Low Byte.
CCh
25h
DMA Channel 7 Current Address High Byte.
CEh
26h
DMA Channel 7 Current Count Low Byte.
CEh
27h
DMA Channel 7 Current Count High Byte.
D0h
28h
DMA Channel 4-7 Status.
Table 30
Alternate Write Access of Normally Read-Only Registers (continued)
I/O ADDRESS
ALTERNATE ACCESS
OFFSET
DESCRIPTION
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