參數(shù)資料
型號： MT8LLN22NCNE
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA316
封裝： 27 X 27 MM, PLASTIC, BGA-316
文件頁數(shù)： 145/145頁
文件大?。?/td> 2285K
代理商： MT8LLN22NCNE
Coppertail Product Specification
MT8LLN22NCNE.fm – Rev. 1, Pub. 2/02
99
2002, Micron Technology Inc.
PRELIMINARY
MT8LLN22NCNE
COPPERTAIL
NOTE:
Register is standby powered and unaffected by SB_POWEROK or P_RST#. Reset only with RSMRST#.
5
APMC_EN. APM Control Enable. When set, enable corresponding status
bit in GLBLSTS to generate an SMI# event. When clear, disable SMI#
event.
R/W
0
4
DEV_EN. Device Status. When set, enable corresponding status bit in
GLBLSTS to generate an SMI# event. When clear, disable SMI# event.
R/W
0
3
SOFTWARE_EN. When set, enable corresponding status bit in GLBLSTS to
generate an SMI# event. When clear, disable SMI# event.
R/W
0
2
MA_EN. Master Abort Enable. When set, enable corresponding status bit
in GLBLSTS to generate an SMI# event. When clear, disable SMI# event.
R/W
0
1
MILLISECOND_EN. When set, enable corresponding status bit in GLBLSTS
to generate an SMI# event. When clear, disable SMI# event.
R/W
0
BIOS_EN. BIOS Status. When set, enable corresponding status bit in
GLBLSTS to generate an SMI# event. When clear, disable SMI# event.
R/W
0
Global Control Register
ADDRESS: ACPI_BASE + 24h
SYMBOL: GLBCTRL
BITS
DESCRIPTION
PROPERTIES
RESET
31
Reserved.
R/W
00000b
30
Enable Key/MSE IRQ capture. When set, enables IRQ1 and IRQ12 to be
captured and held to the 8259’s until a Port 60h read or capture clear
occurs. When clear IRQ1 and IRQ12 are not captured and held to the
8259’s.
R/W
0
29
Enable port 60h Key/MSE IRQ capture clear. When set, enables port 60h
reads to clear the IRQ1 and IRQ12 capture registers. When clear, only the
Clear Key/ MSE IRQ capture bit will clear the capture registers.
R/W
0
28
Clear Key/MSE IRQ capture. Clears the IRQ1 and IRQ12 capture registers.
R/W
0
27
USB_IRQ12_DTCTD. USB IRQ12 status. Set when the USB controller sets
IRQ12.
R/WOTC
0
26
USB_IRQ1_DTCTD. USB IRQ1 status. Set when the USB controller sets
IRQ1.
R/WOTC
0
25
PS2_IRQ12_DTCTD. PS2 IRQ12 status. Set when the PS2 controller sets
IRQ12 off of the L_SERIRQ.
R/WOTC
0
24
PS2_IRQ1_DTCTD. PS2 IRQ1 status. Set when the PS2 controller sets IRQ1
off of the L_SERIRQ.
R/WOTC
0
23:17
USB Legacy BIOS scratch pad.
R/W
0
16
EOSMI. End of SMI. Set on the assertion of SMI#. When clear, I/O control-
ler is enabled to assert an SMI#. WOTC will result in the SMI# not being
asserted for 4 PCI clocks.
R/WOTC
0
15:8
Scratch Register.
R/W
0
Global Enable Register (continued)
ADDRESS: ACPI_BASE + 22h
SYMBOL: GLBEN
BITS
DESCRIPTION
PROPERTIES
RESET
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