- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371133 > MPC105 (MOTOROLA INC) 32-Bit Microprocessor(32位微處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC105 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 存儲(chǔ)控制器/管理單元 |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 1G X 8, DRAM CONTROLLER, PBGA304 |
| 封裝： | BGA-304 |
| 文件頁(yè)數(shù)： | 246/311頁(yè) |
| 文件大?。?/td> | 1708K |
| 代理商： | MPC105 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)當(dāng)前第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)第310頁(yè)第311頁(yè)
8-4
MPC105 PCIB/MC User's Manual
MOTOROLA
8.1.2.1 Processor-Read-from-PCI Buffer (PRPRB)
60x processor reads from PCI require buffering for two primary reasons. First, the
processor bus uses a critical-word-first protocol, while the PCI bus uses a zero-word-first
protocol. The MPC105 requests the data zero-word-first, latches the requested data, and
then delivers the data to the 60x processor critical-word first.
The second reason is that if the target for a processor read from PCI disconnects part way
through the data transfer, the MPC105 may have to handle a system memory access from
an alternate PCI master before the disconnected transfer can continue.
When the processor requests data from the PCI space, the data received from PCI is stored
in the PRPRB until all requested data has been latched. The MPC105 does not terminate
the address tenure of the 60x transaction until all requested data is latched in the PRPRB.
If the PCI target disconnects in the middle of the data transfer and an alternate PCI master
acquires the bus and initiates a read from system memory, the MPC105 retries the 60x
processor so that the incoming PCI transaction can be snooped. A PCI-initiated read from
system memory may require a snoop transaction on the 60x processor bus, and a copy-back
may be necessary.
The PCI interface of the MPC105 continues to request the PCI bus until the processor’s
original request is completed. When the next processor transaction starts, the address is
snooped against the address of the previous transaction (in the internal address buffer) to
verify that the same data is being requested. Once all the requested data is latched, the
MPC105 asserts AACK and DBG
n
(as soon as the 60x data bus is available) and completes
the data transfer to the processor. If a second processor starts a new transaction, the address
cannot match the disconnected transaction address. If the new transaction is not a read from
PCI, it proceeds normally; if the transaction is a read from PCI, it must wait until the
disconnected transaction completes before proceeding.
For example, if the processor initiates a critical-word-first burst read, starting with the
second double word of the cache line, the read on the PCI bus begins with the cache-line-
aligned address. If the PCI target disconnects after transferring the first half of the cache
line, the MPC105 re-arbitrates for the PCI bus, and when granted, initiates a new
transaction with the address of the third double word of the line. If an alternate PCI master
requests data from system memory while the MPC105 is waiting for the PCI bus grant, the
MPC105 retries the processor transaction to allow the PCI-initiated transaction to snoop the
processor bus. When the processor snoop is complete, the subsequent processor transaction
is compared to the latched address and attributes of the PCI read buffer to ensure that the
processor is requesting the same data. Once all data requested by the processor is latched
in the PCI read buffer, the data is transferred to the processor, completing the transaction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC106ARX66CE | PCI Bridge/Memory Controller |
| MPC106ARX66CG | PCI Bridge/Memory Controller |
| MPC106ARX66DE | PCI Bridge/Memory Controller |
| MPC106ARX66DG | PCI Bridge/Memory Controller |
| MPC106ARX66TE | PCI Bridge/Memory Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC1055L1R0C | 制造商:KEMET Corporation 功能描述: 制造商:KEMET Corporation 功能描述:INDUCTOR POWER 1UH 20% SMD - Tape and Reel 制造商:KEMET Corporation 功能描述:Fixed Inductors 1uH 20% SMD |
| MPC1055LR36C | 制造商:KEMET Corporation 功能描述: 制造商:KEMET Corporation 功能描述:INDUCTOR POWER 0.36UH 20% SMD - Tape and Reel 制造商:NEC TOKIN Corporation 功能描述:MPC Series 0.36uH 20% Unshielded SMD Power Inductor 制造商:KEMET Corporation 功能描述:Fixed Inductors 0.36uH 20% SMD |
| MPC106 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller |
| MPC106ARX66CE | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:PCI Bridge/Memory Controller |
| MPC106ARX66CG | 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。