- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371016 > MC145572 (Motorola, Inc.) ISDN U-Interface Transceiver(ISDN U接口收發(fā)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | MC145572 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN U-Interface Transceiver(ISDN U接口收發(fā)器) |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)U型接口收發(fā)器（綜合業(yè)務(wù)數(shù)字網(wǎng)ü接口收發(fā)器） |
| 文件頁(yè)數(shù)： | 61/264頁(yè) |
| 文件大?。?/td> | 2832K |
| 代理商： | MC145572 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)當(dāng)前第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)
MC145572
4–25
MOTOROLA
Select Dump Access
This bit hides the normal byte register BR13, and the register becomes a byte–wide access port, OR13,
to the dump/restore mechanism of the U–chip. Two more bits in the overlay registers control the operat-
ing mode of the dump/restore mechanism. See Overlay register OR8. This bit is reset by hardware
reset only.
Select DCH Access
This bit hides the normal byte register, BR12, and the register becomes an 8–bit read–only/write–only
register, OR12, and provides access to the D channel. When this bit is asserted, D channel input
data present on the pin interfaces of the MC145572 is ignored and Dout is high impedance. Instead,
the D channel is sourced strictly from this register. D channel data received from the U–interface main-
tains correct byte alignment relative to the U–interface basic frame boundary on the pin interfaces,
and is readable through the overlay register, OR12, eight bits at a time. IRQ3 is used to indicate when
every new eight bits of data are received, in addition to indicating a change in receive status.
A special code (1111) is loaded in Nibble register NR1, to indicate that the source of the interrupt
is the D channel access register. Both transmit and receive of the D channel data is aligned respective
to the transmit and receive superframes. When selected, the D channel access register has the highest
priority over other possible routes (e.g., the IDL2 interface and the D channel port), for the D channel
data. This bit is reset by hardware reset only. Software should read and write this register at the time
the D channel interrupt occurs.
Enabling OR12 access, enables the D channel interrupt onto IRQ3. The interrupt must still be enabled
via IRQ3 Enable in NR4 for the IRQ pin to become active. Upon receipt of the interrupt, the external
controller must read the interrupt status in NR3 to determine that it is an IRQ3. The controller must
then read NR1, where it would find the code 1111, indicating the actual source is a D channel interrupt.
NOTE
If DCH Access mode is used in conjunction with timeslot assignment, the D channel time-
slot must not be timeslot 0 in order to maintain synchronization with the transmit super-
frame. This is especially true in LT mode when SFAX is used as an input.
Select Overlay
This bit hides the normal byte registers BR0 – BR9, and the registers become the overlay registers
OR0 – OR9. In general, the overlay registers contain device information that needs to be set only
once following reset, such as the timeslot information or during some test mode. This bit is reset by
hardware reset only.
This register contains activation state and control data. All the bits are cleared on Hardware Reset
(RESET) and Software Reset (NR0(b3)). The register is a read–only/write–only register. Setting
BR14(b6) to 1 permits the external microcontroller to read back the write portion of the register.
b7
b6
b5
b4
b3
b2
b1
b0
BR11
Activation
Control 6
Activation
Control 5
Activation
Control 4
Activation
Control 3
Activation
Control 2
Activation
Control 1
Activation
Control 0
Activation
Timer
Disable
wo
wo
wo
wo
wo
wo
wo
wo
Activation
State 6
Activation
State 5
Activation
State 4
Activation
State 3
Activation
State 2
Activation
State 1
Activation
State 0
Activation
Timer
Expire
ro
ro
ro
ro
ro
ro
ro
ro
Activation Control 6:0
These write–only bits allow the external microcontroller to set a new activation state for the U–interface
transceiver to execute. The transition to this state is controlled by BR12. Use of this register is not
required for normal operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145576 | ISDN NT1(ISDN 網(wǎng)絡(luò)終端) |
| MC14557BCL | 1-to-64 Bit Variable Length Shift Register |
| MC14557BFEL | 1-to-64 Bit Variable Length Shift Register |
| MC14557BDWR2 | RJZ Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 09V; Output Voltage (Vdc): 12V; Power: 2W; 2W Single and Dual Outputs in DIP 14; 3kVDC and 4kVDC Isolation; Optional Continuous Short Circuit Protected; Custom Solutions Available; UL94V-0 Package Material; Efficiency up to 85% |
| MC14557 | 1-to-64 Bit Variable Length Shift Register |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145572AAC | 功能描述:IC TRANSCEIVER ISDN 44-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145572ACR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Freescale Semiconductor 功能描述: |
| MC145572AEI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Freescale Semiconductor 功能描述: |
| MC145572AFN | 功能描述:IC TRANSCEIVER ISDN 44-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145572APB | 功能描述:IC ISDN INTERFACE TXCVER 44-LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。