參數(shù)資料
型號(hào)： MC145572
廠商： Motorola, Inc.
英文描述： ISDN U-Interface Transceiver(ISDN U接口收發(fā)器)
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)U型接口收發(fā)器（綜合業(yè)務(wù)數(shù)字網(wǎng)ü接口收發(fā)器）
文件頁(yè)數(shù)： 119/264頁(yè)
文件大?。?/td> 2832K
代理商： MC145572
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MC145572
7–3
MOTOROLA
ANSI T1.601–1992 indicates that data transparency may occur during the last superframe having its
act
bit equal to 0 or during the first superframe having its
act
bit equal to 1.
In the NT mode of operation, the M4
dea
bit is checked for a 0 and the logical OR of Verified
dea
,
BR3(b1), and deactivation Request, NR2(b2), ensures that the NT U–interface transceiver deactivates
in a controlled manner and will reactivate in warm start mode on a subsequent activation attempt.
An interrupt is generated when BR1 is updated, if Enable IRQ1, NR4(b1), is set to a 1.
M4 Control mode 0,1 is the dual consecutive mode of operation. BR1 is updated when the Superframe
Deframer detects that an M4 subchannel bit has changed state and has remained in that state for
two consecutive superframes and Superframe Sync, NR2(b1), is set to a 1. An interrupt is generated
at this time, if Enable IRQ1, NR4(b1), is set to a 1.
M4 Control mode 1,0 is the delta mode of operation. The M4 channel register is updated with new
M4 channel data whenever any single bit changes between received M4 frames. An interrupt is gener-
ated at this time, if Enable IRQ1, NR4(b1), is set to a 1.
M4 Control mode 1,1 updates the M4 channel register BR1 on every received superframe. In this
mode, the Superframe Deframer does not check for a change in data between received M4 frames.
An interrupt is generated at this time, if Enable IRQ1, NR4(b1), is set to a 1.
The M5 and M6 channels operate in the same modes as the M4 channel bits, except for the automatic
verification mode. The received M5 and M6 data from the Superframe Deframer is available in BR2.
See BR9 for details on the operating modes of the M5 and M6 channels. These channels are configured
as a pair. An interrupt is generated when BR2 is updated and Enable IRQ0, NR4(b0), is set to a 1.
As defined by ANSI T1.601–1992, these are reserved maintenance channels and should be initialized
to 1s. The M5 and M6 maintenance channels are available for proprietary applications which do not
have to comply with ANSI T1.601.
febe
nebe
The MC145572 has extensive
febe
and
nebe
maintenance capabilities. The state of the received
computed
nebe
and of the received
febe
is available through the register interface. Also, two indepen-
dent
febe
and
nebe
counters are available for performance monitoring purposes.
The received
febe
from the last completed superframe is available in Received
febe
, BR3(b4). It
is updated at the end of each superframe when both Superframe Sync and Linkup, NR1(b3, b1), are
set to a 1.
The
febe
/
nebe
Control bit, BR9(b1), controls operation of the transmitted
febe
status bit. When
BR9(b1) is set to a 1, the transmitted
febe
bit is set to whatever is set in the
febe
input, BR2(b4).
When BR9(b1) is reset to a 0, the transmitted
febe
is set active, if the computed
nebe
is active or
if
febe
input, BR2(b4), is active. In this case, “active” means 0. BR9(b1) reset to 0 is the normal mode
of operation and no intervention is required by an external MCU for the MC145572 to send the outgo-
ing
febe
bit.
In NT and LT mode operation when BR9(b1) is set to a 1, BR2(b4) must be cleared to a 0 at the
end of reception of basic frame 8 when it is desired to force an outgoing
febe
. BR2(b4) must be
set to a 1 at the end of reception of basic frame 8 when no outgoing
febe
is required. Software should
always configure BR2(b4) for the correct outgoing
febe
once each superframe. In digital loop carrier
applications, this guarantees that there will be a one–to–one correspondence between the
febe
status received from the digital carrier system and the
febe
transmitted on the U–interface. The
febe
is transmitted at the end of basic frame 2. See Figure 7–1 and
Section 7.7
for interrupt timing
information.
The computed
nebe
of the last completed superframe is available in Computed
nebe
, BR3(b3). This
bit is set or cleared as a result of a
crc
of the last superframe received. This bit is updated at the
end of each superframe. The Computed
nebe
is reset to a 0 when a
crc
error is detected, and is
set to a 1 when no
crc
error is detected. When either Superframe Sync or Linkup, NR1(b3, b1), are
reset to a 0, the Computed
nebe
bit is forced to a 0.
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