參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 86/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
2- 12
Advanced v0.5
Clock Aggregation
Clock aggregation allows for multi-spine clock domains.
A MUX tree provides the necessary flexibility to allow
long lines or I/Os to access domains of one, two, or four
global spines. Signal access to the clock aggregation
system is achieved through long-line resources in the
central rib, and also through local resources in the north
and south ribs, allowing I/Os to feed directly into the
clock system. As Figure 2-12 indicates, this access system
is contiguous.
There is no break in the middle of the chip for the north
and south I/O VersaNet access. This is different from the
quadrant clocks located in these ribs, which only reach
the middle of the rib. Refer to the Using Global
Figure 2-11 Spine Selection MUX of Global Tree
Figure 2-12 Clock Aggregation Tree Architecture
Internal/External
Signal
Internal/External
Signal
Internal/External
Signals
Spine
Global Rib
Global Driver MUX
Tree Node MUX
Internal/External
Signals
Tree Node MUX
Global Spine
Global Rib
Global Driver and MUX
I/O Access
Internal Signal Access
I/O Tiles
Global Signal Access
Tree Node MUX
相關(guān)PDF資料
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