參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 68/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
2- 4
A dvanced v0. 5
Array Coordinates
During many place-and-route operations in the Actel
Designer software tool, it is possible to set constraints
that require array coordinates. Table 2-1 provides array
coordinates of core cells and memory blocks. The array
coordinates are measured from the lower left (0, 0). They
can be used in region constraints for specific logic
groups/blocks, designated by a wildcard, and can contain
core cells, memories, and I/Os.
I/O and cell coordinates are used for placement
constraints. Two coordinate systems are needed because
there is not a one-to-one correspondence between I/O
cells and core cells. In addition, the I/O coordinate system
changes depending on the die/package combination. It is
not listed in Table 2-1. The Designer ChipPlanner tool
provides array coordinates of all I/O locations. I/O and
cell coordinates are used for placement constraints.
However, I/O placement is easier by package pin
assignment.
Figure 2-4 illustrates the array coordinates of an A3PE600
device. For more information on how to use array
coordinates for region/placement constraints, see the
Designer User's Guide or online help (available in the
software) for ProASIC3E software tools.
Table 2-1 ProASIC3E Array Coordinates
Device
VersaTiles
Memory Rows
All
Min.
Max.
Bottom
Top
Min.
Max.
x
y
x
y
(x, y)
A3PE600
3
4
194
75
(3, 2)
(3, 76)
(0, 0)
(197, 79)
A3PE1500
3
4
322
123
(3, 2)
(3, 124)
(0, 0)
(325, 127)
A3PE3000
3
6
450
173
(3, 2) or (3, 4)
(3, 174) or (3, 176)
(0, 0)
(453, 179)
Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates
are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}.
Figure 2-4 Array Coordinates for A3PE600
Top Row (5, 1) to (168, 1)
Bottom Row (7, 0) to (165, 0)
Top Row (169, 1) to (192, 1)
I/O Tile
Memory
Blocks
Memory
Blocks
Memory
Blocks
UJTAG FlashROM
Top Row (7, 79) to (189, 79)
Bottom Row (5, 78) to (192, 78)
I/O Tile
(3, 77)
(3, 76)
Memory
Blocks
(3, 3)
(3, 2)
VersaTile (Core)
(3, 75)
VersaTile (Core)
(3, 4)
(0, 0)
(197, 0)
(194, 2)
(194, 3)
(194, 4)
VersaTile (Core)
(194, 75)
VersaTile (Core)
(197, 79)
(194, 77)
(194, 76)
(0, 79)
(197, 1)
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