參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 10/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-39
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer
and an open drain output buffer. The VCCI pin should be connected to 2.5 V.
Timing Characteristics
Table 3-53 Minimum and Maximum DC Input and Output Levels
2.5 V GTL+
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive Strength Min, V
Max, V
Min, V
Max, V Max, V Min, V
mA
Max, mA1 Max, mA1
A2 A2
33 mA
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.6
–
33
124
169
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 3-14 AC Loading
Table 3-54 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
VTT (Typ) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
1.0
1.5
10
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Test Point
10 pF
25
GTL+
V
TT
Table 3-55 2.5 V GTL+
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V, VREF = 1.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
–F
0.72
2.65
0.05
1.82
0.51
2.70
2.52
5.38
5.21
ns
Std.
0.60
2.21
0.04
1.51
0.43
2.25
2.10
4.48
4.34
ns
–1
0.51
1.88
0.04
1.29
0.36
1.91
1.79
3.81
3.69
ns
–2
0.45
1.65
0.03
1.13
0.32
1.68
1.57
3.35
3.24
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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