參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 116/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-39
Solution 2
The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4
on page 3-2. This is a requirement to ensure long term reliability.
This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,
and the voltage must be limited by the external resistors and zener, as shown in Figure 2-27. Relying on the diode
clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.
Figure 2-27 Solution 2
Solution 2
5.5 V
3.3 V
Requires one board resistor, one
Zener 3.3 V diode, LVCMOS 3.3 V I/Os
ProASIC3E I/O Input
Rext1
Zener
3.3V
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