參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 104/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
2- 28
Advanced v0.5
inputs and outputs, with register enable if desired
(Figure 2-23 on page 2-33). The registers can also be used
to support the JESD-79C Double Data Rate (DDR)
standard within the I/O structure (see the "Double Data
information).
As depicted in Figure 2-23 on page 2-33, all I/O registers
share one CLR port. The output register and output
enable register share one CLK port. Refer to the "I/O
I/O Banks and I/O Standards Compatibility
I/Os are grouped into I/O voltage banks. There are eight I/O
banks (two per side). Each I/O voltage bank has a dedicated
input/output supply and ground voltages (VMV/GNDQ for
input buffers and VCCI/GND for output buffers). Because of
these dedicated supplies, only I/Os with compatible
standards can be assigned to the same I/O voltage bank.
Table 2-12 on page 2-29 shows the required voltage
compatibility values for each of these voltages.
For more information about I/O and global assignments
to I/O banks, refer to the specific pin table of the device
Every I/O bank is divided into minibanks. Any user I/O in a
VREF minibank (a minibank is the region of scope of a
VREF pin) can be configured as a VREF pin (Figure 2-22).
Only one VREF pin is needed to control the entire VREF
minibank. The location and scope of the VREF minibanks
can be determined by the I/O name. For details, see the
shows the I/O standards
supported by ProASIC3E devices and the corresponding
voltage levels.
I/O standards are compatible if:
Their VCCI and VMV values are identical
Both of the standards need a VREF and their VREF
values are identical
Figure 2-22 Typical I/O Bank Detail Showing VREF Minibanks
CCC/PLL
“C”
CCC/PLL
“D”
CCC/PLL
“B”
Bank
3
Bank
2
JTAG
Common V
REF
signal for all I/Os
in V
REF minibanks
Up to five V
REF
minibanks within
an I/O bankF
Any I/O in a V
REF
minibank can be used to
provide the reference
voltage to the common
V
REF signal for the V
REF
minibank.
V
REF signal scope is
between 8 and 18 I/Os.
I/O
Vcci
GND
Vcc
I/O
Vcci
GND
Vcc
I/O
I/O Pad
CCC/PLL
"C"
CCC/PLL
"D"
CCC/PLL
"B"
Bank
3
Bank
2
JTAG
I/O
Vcci
V
CCI
GND
Vcc
V
CC
I/O
Vcci
GND
Vcc
I/O
V
CCI
V
CC
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