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| 型號(hào)： | M7A3PE600-FFGG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PBGA484 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-484 |
| 文件頁(yè)數(shù)： | 130/168頁(yè) |
| 文件大?。?/td> | 1335K |
| 代理商： | M7A3PE600-FFGG484I |
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ProASIC3E Flash Family FPGAs
2- 52
Advanced v0.5
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly
pulled up to VCCI. With VCCI, VMV, and VCC supplies
continuously powered-up, and the device transitions
from programming to operating mode, the I/Os get
instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of Hi-Z)
Input buffer is disabled (with tristate value of Hi-Z)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as Pro I/Os, since they have identical capabilities.
Unused GL pins are configured as inputs with pull-up
resistors.
Refer to the "User I/O Naming Convention" section on
page 2-50 for a explanation of the naming of global
pins.
JTAG Pins
ProASIC3E devices have a separate bank for the
dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). VCC must also be
powered in order for the JTAG state-machine to operate
even if the device is in bypass mode; VJTAG alone is
insufficient. Both VJTAG and VCC to the ProASIC3E part
must be supplied to allow JTAG signals to transition the
ProASIC3E device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility with supply
selection and simplifies power supply and printed circuit
board design. If the JTAG interface is neither used nor
planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK
Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG.
The TCK pin does not have an internal pull-up/down
resistor. Actel recommends adding a nominal 20 k
pull-
up resistor to this pin. If JTAG is not used, Actel
recommends tying off TCK to GND or VJTAG through a
resistor placed close to the FPGA pin. This prevents JTAG
operation in case TMS enters an undesired state.
Note that to operate at all VJTAG voltages, 500 to 1 k
will satisfy the requirements. Refer to Table 2-24 for
more information.
Note that to operate at all VJTAG voltages, 500 to 1 k
will satisfy the requirements.
TDI
Test Data Input
Serial input for JTAG boundary scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
TDO
Test Data Output
Serial output for JTAG boundary scan, ISP, and UJTAG
usage.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE1532 boundary
scan pins (TCK,TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
TRST
Boundary Scan Reset Pin
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the
TRST pin. If JTAG is not used, an external pull-down
resistor could be included to ensure the TAP is held in
reset mode. The resistor values must be chosen from
Table 2-24 and must satisfy the parallel resistance value
requirement. The values in Table 2-24 correspond to the
resistor recommended when a single device is used and
the equivalent parallel resistor when multiple devices are
connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could
allow entering an undesired JTAG state. In such cases,
Actel recommends tying off TRST to GND through a
resistor placed close to the FPGA pin.
Note that to operate at all VJTAG voltages, 500 to 1 k
will satisfy the requirements.
Table 2-24 Recommended Tie-Off Values for the TCK and
TRST Pins
VJTAG
Pull-Down Resistance*
VJTAG at 3.3 V
200
to 1 k
VJTAG at 2.5 V
200
to 1 k
VJTAG at 1.8 V
500
to 1 k
VJTAG at 1.5 V
500
to 1 k
Notes:
1. Equivalent parallel resistance if more than one device is on
JTAG chain.
2. The TSK pin can be pulled up/down.
3. The TRST pin can only be pulled down.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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