參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 18/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
3- 46
Advanced v0.5
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is
handled by the Actel Designer software when the user
instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the
embedded Input Register (InReg), Output Register
(OutReg), Enable Register (EnReg), and Double Data
Rate
(DDR).
However,
there
is
no
support
for
bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a
high-speed, differential I/O standard. It requires that one
data bit is carried through two signal lines; so two pins
are needed. It also requires external resistor termination.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 3-21. The
building blocks of the LVDS transmitter-receiver are one
transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVPECL implementation,
because the output standard specifications are different.
Along with the LVDS I/O, ProASIC3E also will support
BusLVDS
structure
and
Multi-Drop
LVDS
(M-LVDS)
configuration (up to 40 nodes).
Figure 3-21 LVDS Circuit Diagram and Board-Level Implementation
Table 3-74 Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Typ.
Max.
Units
VCCI
Supply Voltage
2.375
2.5
2.625
V
VOL
Output Low Voltage
0.9
1.075
1.25
V
VOH
Output High Voltage
1.25
1.425
1.6
V
VI
Input Voltage
0
–
2.925
V
VODIFF
Differential Output Voltage
250
350
450
mV
VOCM
Output Common Mode Voltage
1.125
1.25
1.375
V
VICM
Input Common Mode Voltage
0.05
1.25
2.35
V
VIDIFF
Input Differential Voltage
100
350
–
mV
Notes:
1. +/- 5%
2. Differential input voltage = +/-350mV
Table 3-75 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.075
1.325
Cross point
–
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
140
100
ZO = 50
ZO = 50
165
165
+
-
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Bourns Part Number: CAT16-LV4F12
相關(guān)PDF資料
PDF描述
M7A3PE600-FPQ208I FPGA, 600000 GATES, PQFP208
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
M7R-R63FAJFREQ CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT
M7R-R68TAJFREQ CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT
M7R76FCJFREQ CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS OUTPUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M7A5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS
M7A9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS
M7AFS600-1FG256 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays
M7AFS600-1FG256ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs
M7AFS600-1FG256I 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*