- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180243 > M7A3PE600-FFGG484I FPGA, 600000 GATES, PBGA484 PDF資料下載
參數(shù)資料
| 型號： | M7A3PE600-FFGG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PBGA484 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-484 |
| 文件頁數(shù)： | 113/168頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | M7A3PE600-FFGG484I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁當(dāng)前第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-37
Grounds
Powers
I/Os and other pins
Cold-Sparing Support
Cold-sparing means that a subsystem with no power
applied (usually a circuit board) is electrically connected
to the system that is in operation. This means that all
input buffers of the subsystem must present very high
input impedance with no power applied so as not to
disturb the operating portion of the system.
ProASIC3E devices support cold-sparing for all I/O
configurations. Standards such as PCI which require I/O
clamp diodes can also achieve cold-sparing compliance,
since clamp diodes get disconnected internally when the
supplies are at 0 V.
If the resistor is chosen, the resistor value must be
calculated based on decoupling capacitance on a given
power supply on the board (this decoupling capacitor is
in parallel with this resistor). The RC time constant
should ensure full discharge of supplies before cold-
sparing functionality is required. The resistor is necessary
to ensure that the power pins are discharged to ground
every time there is an interruption of power to the
device.
Electrostatic Discharge (ESD) Protection
ProASIC3E devices are tested per JEDEC Standard
JESD22-A114-B.
ProASIC3E devices contain clamp diodes at every I/O,
global, and power pad. Clamp diodes protect all device
pads against damage from ESD as well as from excessive
voltage transients.
ProASIC3E devices are tested to the following models:
Human Body Model (HBM) with a tolerance of 2,000 V,
the Machine Model (MM) with a tolerance of 250 V, and
the Charged Device Model (CDM) with a tolerance of
200 V.
Each I/O has two clamp diodes. One diode has its
positive (P) side connected to the pad and its negative
(N) side connected to VCCI. The second diode has its P
side connected to GND, and its N side connected to the
pad. During operation, these diodes are normally
biased in the Off state, except when transient voltage is
significantly above VCCI or below GND levels.
By selecting the appropriate I/O configuration, the diode
is turned on or off. Refer to Table 2-18 for more
information about the I/O standards and the clamp
diode.
The second diode is always connected to the pad,
regardless of the I/O configuration selected.
Table 2-18 I/O Hot-Swap and 5 V Input Tolerance Capabilities
I/O Assignment
Clamp
Diode
Hot
Insertion
5 V Input
Tolerance Input Buffer
Output
Buffer
3.3 V LVTTL/LVCMOS
No
Yes
Yes1
Enabled/Disabled
3.3 V PCI, 3.3 V PCI-X
Yes
No
Yes1
Enabled/Disabled
LVCMOS 2.5 V 3
No
Yes
No
Enabled/Disabled
LVCMOS 2.5 V / 5.0 V 3
Yes
No
Yes2
Enabled/Disabled
LVCMOS 1.8 V
No
Yes
No
Enabled/Disabled
LVCMOS 1.5 V
No
Yes
No
Enabled/Disabled
Voltage-Referenced Input Buffer
No
Yes
No
Enabled/Disabled
Differential, LVDS/BLVDS/M-LVDS/LVPECL
No
Yes
No
Enabled/Disabled
Notes:
1. Can be implemented with an external IDT bus switch, resistor divider, or zener with resistor.
2. Can be implemented with an external resistor and an internal clamp diode.
3. In the SmartGen Core Reference Guide, select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25
macro for the LVCMOS 2.5 V I/O standard.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M7A3PE600-FPQ208I | FPGA, 600000 GATES, PQFP208 |
| M7A3PE600-FPQG208I | FPGA, 600000 GATES, PQFP208 |
| M7R-R63FAJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT |
| M7R-R68TAJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT |
| M7R76FCJFREQ | CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。