參數(shù)資料
型號(hào)： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 137/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
3- 2
A dvanced v0. 5
Table 3-2
Recommended Operating Conditions
Symbol
Parameter
Commercial
Industrial
Units
TA, TJ
Ambient and Junction temperature
0 to +70
–40 to +85
°C
VCC
1.5 V DC core supply voltage
1.425 to 1.575
V
VJTAG
JTAG DC voltage
1.4 to 3.6
V
VPUMP
Programming voltage
Programming Mode
3.0 to 3.6
V
Operation3
0 to 3.6
V
VCCPLL
Analog power supply (PLL)
1.4 to 1.6
V
VCCI and VMV 1.5 V DC supply voltage
1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
V
LVDS/BLVDS/M-LVDS differential I/O
2.375 to 2.625
V
LVPECL differential I/O
3.0 to 3.6
V
Notes:
1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given
in Table 3-13 on page 3-15. VMV and VCCI should be at the same voltage within a given I/O bank.
2. All parameters representing voltages are measured with respect to GND unless otherwise specified.
3. VPUMP can be left floating during normal operation (not programming mode).
Table 3-3 Flash Programming Limits - Retention, Storage and Operating Temperature1
Product Grade
Programming
Cycles
Program Retention
(Biased/Unbiased)
Maximum Storage
Temperature TSTG (°C)
2
Maximum Operating Junction
Temperature TJ (°C)
2
Commercial
500
20 years
110
Industrial
500
20 years
110
Notes:
1. This is a stress rating only, functional operation at any other condition other than those indicates is not implied.
2. These limits apply for program/data retention only. Refer to tables 3-1 and 3-2 for device operating conditions and absolute limits.
Table 3-4
Overshoot and Undershoot Limits (as measured on quiet I/Os)1
VCCI and VMV
Average VCCI-GND Overshoot or Undershoot Duration as a
Percentage of Clock Cycle2
Maximum Overshoot/
Undershoot)2
2.7 V or less
10%
1.4 V
5%
1.49 V
3 V
10%
1.1 V
5%
1.19 V
3.3 V
10%
0.79 V
5%
0.88 V
3.6 V
10%
0.45 V
5%
0.54 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one cycle out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at
1 out of 2 cycles, then the maximum overshoot/undershoot has to be reduced by 0.15 V.
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