參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 20/168頁
文件大小： 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
3- 48
Advanced v0.5
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is
another differential I/O standard. It requires that one
data bit is carried through two signal lines. Like LVDS,
two pins are needed. It also requires external resistor
termination.
The full implementation of the LVDS transmitter and
receiver is shown in an example in Figure 3-23. The
building blocks of the LVPECL transmitter-receiver are
one transmitter macro, one receiver macro, three board
resistors at the transmitter end, and one resistor at the
receiver end. The values for the three driver resistors are
different from those used in the LVDS implementation,
because the output standard specifications are different.
Timing Characteristics
Figure 3-23 LVPECL Circuit Diagram and Board-Level Implementation
Table 3-77 Minimum and Maximum DC Input and Output Levels
DC Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage
3.0
3.3
3.6
V
VOL
Output Low Voltage
0.96
1.27
1.06
1.43
1.30
1.57
V
VOH
Output High Voltage
1.8
2.11
1.92
2.28
2.13
2.41
V
VIL, VIH
Input Low, Input High voltages
0
3.3
0
3.6
0
3.9
V
VODIFF
Differential Output Voltage
0.625
0.97
0.625
0.97
0.625
0.97
V
VOCM
Output Common Mode Voltage
1.762
1.98
1.762
1.98
1.762
1.98
V
VICM
Input Common Mode Voltage
1.01
2.57
1.01
2.57
1.01
2.57
V
VIDIFF
Input Differential Voltage
300
mV
Table 3-78 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
1.64
1.94
Cross point
–
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Table 3-79 LVPECL
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
Speed Grade
tDOUT
tDP
tDIN
tPY
Units
–F
0.79
2.19
0.05
1.96
ns
Std.
0.66
1.83
0.04
1.63
ns
–1
0.56
1.55
0.04
1.39
ns
–2
0.49
1.36
0.03
1.22
ns
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
187 W
100
ZO = 50
ZO = 50
100
100
+
-
P
N
P
N
INBUF_LVPECL
OUTBUF_LVPECL
FPGA
Bourns Part Number: CAT16-PC4F12
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