參數(shù)資料
型號： M7A3PE600-FFGG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù)： 81/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG484I
ProASIC3E Flash Family FPGAs
ii
Advanced v0. 5
I/Os Per Package1
ProASIC3E Devices
A3PE600
A3PE1500 3
A3PE3000 3
ARM-Enabled
ProASIC3E Devices
M7A3PE600
M7A3PE1500
M7A3PE3000
Package
I/O Types
Single-Ended
I/O1
Differential
I/O Pairs
Single-Ended
I/O1
Differential
I/O Pairs
Single-Ended
I/O1
Differential
I/O Pairs
PQ208
147
65
147
65
147
65
FG256
165
79
–
FG484
270
135
280
136
280
136
FG676
–
439
209
–
FG896
–
616
300
Notes:
1. When considering migrating your design to lower or higher density devices, refer to the "Package Pin Assignments" section on
page 4-1 to ensure complying with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited:
– SSTL3(I) and (II): up to 40 I/Os per north or south bank
– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank
– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
4. FG256 and FG484 are footprint-compatible packages.
5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank
(group of I/Os). Refer to the "I/O Banks and I/O Standards Compatibility" section on page 2-28 for more information about VREF and
the use of minibanks.
相關(guān)PDF資料
PDF描述
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