參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 52/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
145 of 162
October 20, 2006
IDT IDT88K8483
Miscellaneous Registers
PMON Timebase Control Register
PMON 1ms Timer Register
GPIO Direction Register
There are 3 registers.Register offset 0x10 is for GPIO 0. Register offset 0x11 is for GPIO 1and register offset 0x12 is for GPIO 2.
Field
Read /
Write
Bits
Length Reset
State
Description
INTERNAL
R/W
0:0
1
0
Selects between the internal and external time base.Please refer to table 144.
TIMER
R/W
0:1
1
0
Selects the internal timer/OBC as the timebase timing source. Please refer to table
144.
MANUAL
R/WC
0:2
1
0
Manual time base trigger, self clear.
Table 156
PMON Timebase Control Register (Block Base=0x8B00, Register Offset=0x00)
Manual
Timer
Internal
Timebase trigger
Bit 2
Bit 1
Bit 0
Source
XX
0
External.
X
1
Internal timer.
X0
1
External OBC.
Table 157 Timebase source table.
Field
Read /
Write
Bits
Length Reset
State
Description
PERIOD
R/W
0:0-2:1
18
0x1E600
The timer register specifies the number of MCLK for generation of a 1ms time
interval.
Table 158
PMON 1ms Timer Register (Block Base=0x8B00, Register Offset=0x01)
Field
Read /
Write
Bits
Length Reset
State
Description
DIR_OUT
R/W
0:0
1
0
This field controls the direction of General Purpose IO pins. The direction can be
input or output.
0: The GPIO pins act as input/read pins.
1: The GPIO pins act as output/write pins.
Table 159
GPIO Direction Register (Block Base=0x8B00, Register Offset=0x10-0x12)
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