參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 12/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
109 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Ingress Diagnostics Register
SPI-4 Ingress Automatic Alignment Control Register
SPI4 Ingress Calendar Switch Control Register
Table 65 SPI-4 Ingress Calendar Switch Control Register (Block base=0x0300, Register Offset=0x08)
Field
Read /
Write
Bits
Length Reset
State
Description
I_FORCE_TRAIN
R/W
0:0
1
0
This field is used to force continuous training on the SPI-4 ingress status interface.
0:Normal status channel operation.
1:Force continuous training on the SPI-4 ingress status interface.
I_ERR_INS
R/W
0:1
1
0
This field is used to insert the number of DIP-2 errors on the SPI-4 ingress status
interface programmed into the I_DIP_NUM field. After the DIP-2 errors are inserted,
the I_ERR_INS field will clear itself.
0:Normal status channel operation.
1:Insert DIP-2 errors on the SPI-4 ingress status interface.
I_DIP_NUM
R/W
0:2-0:5
4
0
This field is used to program the number of DIP-2 errors to be inserted when the
field I_ERR_INS is set to ‘1’. The number programmed should be less than 16.
Note: The purpose of the status channel training sequence is for the deskew of status and clock signals and for the alignment between the 2 status signals.
Table 63
SPI-4 Ingress Diagnostics Register (Block base=0x0300, Register Offset=0x06)
Field
Read /
Write
Bits
Length Reset
State
Description
AUTO_ALIGN
R/W
0:0
1
0
This field enables or disables automatic alignment for the incoming LVDS data bits
in the data path. This register is used for test purposes.
0:Auto alignment is used for test mode.
1:Auto alignment is automatic.
Table 64
SPI-4 Ingress Automatic Alignment Control Register (Block base=0x0300, Register Offset=0x07)
Field
Read /
Write
Bits
Length
Reset
State
Description
I_CSW_EN
R/W
0:0
1
0
The I_CSW_EN field is used to enable the switching of active calendars and
works together with CAL_SEL.Refer to Table 66 for calendar selection.
CAL_SEL
R/W
0:1
1
0
This field is used to select calendar_0 or calendar_1. This bit is valid only if
I_CSW_EN is set to 1. Refer to Table 66 for calendar selection.
I_DIP_CSW
R/W
0:2
1
This field describes the DIP-2 computation method based on the setting of
I_CSW_EN.Please refer toTable 67 for bit setting.
Note: Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) for more details about calendar implementation.
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IDT88P8341BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝
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