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參數(shù)資料
| 型號： | IDT88K8483BRI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 101/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI-4 EXCHANGE 3PORT 672-BGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88K8483BRI |
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October 20, 2006
IDT IDT88K8483
Figure 15 SPI-4 Ingress Block Diagram
Bit alignment
The bit alignment block is responsible for data and clock alignment. The bit alignment allows the clock to be used for correct data sampling and
eliminate bit errors by providing adequate set-up and hold time margins.
The alignment selection is programed by AUTO_ALIGN field in the SPI-4 Ingress Automatic Alignment Control Register (p. 109). The device is
responsible for an edge transition histogram for each lane (lane is defined as a deferential pair of data, control or status signals). The data is sampled
by 10-phased-shifted clock during each clock cycle. Each 2 consecutive sampled values are XORed and accumulated during a fixed observation
window to generate transition edge histogram.
The measurement histogram is triggered by writing to the LANE field in the SPI-4 Histogram Measure Launch Register (p. 117). The measurement
process is indicated by the BUSY field in the SPI-4 Histogram Measure Status Register (p. 117). The BUSY field is set to 1 when a measurement is
launched. The BUSY field is auto cleared to 0 when the measure is finished. The received bit stream is selected from the 10 samples. The tap selec-
tion is made automatically and is available in the TAP_SEL field in the SPI-4 Bit Alignment Result Register (p. 118).
The bit alignment sequence automatically carried out in the device as follows:
- Write lane number in the LANE field in the SPI-4 Histogram Measure Launch Register (p. 117).
- Poll the BUSY field in the SPI-4 Histogram Measure Status Register (p. 117). If BUSY is 0, then read the C[n] field in the SPI-4 Histogram Counter
Register (p. 117) which indicates the counter value. The counter value is used to select the tap.
- Write the selected Tap value to TAP field in the SPI-4 Bit Alignment Result Register (p. 118).
De-skew
The De-skew block is responsible for alignment between the data signals. The De-skew block can de-skew +/-1bit. For diagnose purpose, an out
of range offset between lines is provided. If the skew is more than 2 bits, then the I_DSK_OOR field in the SPI-4 Ingress Status Register (p. 108) is
set. The I_DSK_OOR field is cleared when the offset is in range.
Receive State Machine
The ingress data channel has 2 states, IN_SYNCH and OUT_OF_SYNCH. The machine transitions from OUT_OF_SYNCH to IN_SYNCH if a
number of consecutive error-free DIP-4 are detected. The number is configured by using the SPI-4 Ingress Configuration Register (p. 106). The
machine stays in OUT_OF_SYNCH state if the interface is not enabled.
The status of the synchronization is indicated by I_SYNCV field in the SPI-4 Ingress Status Register (p. 108). Any transition on I_SYNCV will be
captured by the PMON Event Interrupt Indication Register (p. 136). An interrupt is generated if interrupt options is enabled. The data channel synchro-
nization status is fed to status channel generation logic for handshaking.
Bit
alignment
Deskew
Rx machine
status
generation
Locker
Skew control
status
PFP
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