- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT88K8483BRI (IDT, Integrated Device Technology Inc)IC SPI-4 EXCHANGE 3PORT 672-BGA PDF資料下載
參數(shù)資料
| 型號： | IDT88K8483BRI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 111/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI-4 EXCHANGE 3PORT 672-BGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88K8483BRI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁當(dāng)前第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁
52 of 162
October 20, 2006
IDT IDT88K8483
Packet Fragment Processor (PFP)
Overview
Figure 20 PFP Block Diagram
The Packet Segment Pool (PFP) is an internal block which is used for queuing and scheduling. There are four PFPs in the device - one for each
SPI-4 tributary port and direction: PFP module A tributary to main (PFP-A-MT), PFP module A main to tributary (PFP-A-MT), PFP module B tributary
to main (PFP-B-MT) and PFP module B main to tributary PFP-B-MT. The PFP includes the ingress server, queues and egress server as described in
. The queues include two types of buffers: data buffer and context buffer. The data buffer stores the payload
and the context buffer stores the payload location in the data buffer. For each PFP, the content buffer has 4K entries which are equal assigned
between the LIDs. For each PFP, the data buffer has 127K bytes, which are divided into 508 segments of 256 bytes. M field in the PFP Buffer
Segment Assign Table (p. 120) configures the number of segments in the data buffer for each LID.
The PFP can be programed to over-booking mode by setting to 1 the OVBK_EN field in the PFP Buffer Management Configuration Register
(p. 123). In non over-booking mode, the segments allocation is static, and the data buffer space is not shared between the LIDs, so the maximum
number of segments for each LID is M. In over booking mode, the segment allocation is dynamic, and the data buffer space can be overlapped
between the LIDs, so the maximum number of segments for each LID is up to 8 times the value of M segments, depending on how much the other
LIDs are occupied. In over- booking mode, it is recommended that back-pressure is not used at the PFP egress in order to avoid deadlock. When
using over-booking mode, the global threshold should be programed in the BUF_THR field in the PFP Buffer Management Configuration Register
The ingress server transfer data from the ingress port buffers to the data buffers. The ingress server sequence is: read ingress port buffer, request
data buffer segment, move data to data buffer and put the payload location information in the context buffer. The ingress server checks the SOP/EOP
sequence. If the ingress server detects SOP-EOP-EOP sequence or EOP-SOP-SOP sequence, then it sends illegal sequence event to PMON. If the
ingress server detects buffer overflow, then it sends over flow event to PMON. If the ingress server detects a too-long packet, then it truncates the
packets, adds SOP/EOP and error tag accordingly, and sends cut-down event to PMON. The packet length is programed in the MAX_LEN field in the
The egress server is responsible for ensuring that per port quality of service is maintained, and it includes the scheduler which has both round
robin priority mode and high/low priority mode. The scheduler schedules segments, or complete packets spanning several segments, from the data
buffer to egress port buffer. The device can be programed to priority mode by setting to 1 the WEIGHT_E field in the PFP Queue Weighting Enable
Register (p. 124). The LID priority can be programmed to high by setting to 1 the WEIGHT field in the PFP Egress Weight And Direction Register
(p. 122). When the priority mode is enabled, the scheduler serves first the high priority segments before the low priority segments. When the priority
mode is enabled, if high priority LID receives starving or hungry status from the egress interface, then the device sets the internal LID status to
starving and uses the starving maximum burst size (MAX_BURST_S field in the PFP Egress Burst Size Table (p. 122)). When the priority mode is
enabled, if low priority LID receives starving or hungry status from the egress interface, then the device sets the internal status to hungry and it uses
the hungry max burst size (MAX_BURST_H field in the PFP Egress Burst Size Table (p. 122)).
The egress has four directions: SPI-4 tributary to SPI-4 main or SPI-4 main to SPI-4 tributary, redirect or loopback, extract and discard. The egress
direction for each LID is programed in the DIR field in the PFP Egress Weight And Direction Register (p. 122). The egress direction can be
programmed on-the-fly, as long as traffic is not present.
Ingress
Server
Egress
Server
SPI-4
Ingress
Port
Buffer
SPI-4
Egress
Port
Buffer
PFP
SPI-4
Egress
Interface
SPI-4
Ingress
Interface
Data Buffer
Context Buffer
Queues
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT88P8341BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| IDT88P8342BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| IDT88P8344BHI | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| IDT89H24NT24G2ZBHLG | IC PCI SW 24LANE 24PORT 324BGA |
| IDT89HPES16NT2ZBBCG | IC PCI SW 16LANE 2PORT 484-CABGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT88P8341BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8341BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT88P8344 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。