參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 45/162頁
文件大?。?/td> 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88K8483BRI
139 of 162
October 20, 2006
IDT IDT88K8483
PMON Event Interrupt Enable Register
Field
Read /
Write
Bits
Length Reset
State
Description
T_INACT_EN
R/W
0:0
1
0
Tributary ingress inactive LP.
0: Disables the interrupt.
1: Enables the interrupt.
M_INACT_EN
R/W
0:1
1
0
Main ingress inactive LP.
0: Disables the interrupt.
1: Enables the interrupt.
TM_ISOP_EN
R/W
0:2
1
0
T-M illegal SOP.
0: Disables the interrupt.
1: Enables the interrupt.
TM_IEOP_EN
R/W
0:3
1
0
T-M illegal EOP.
0: Disables the interrupt.
1: Enables the interrupt.
MT_ISOP_EN
R/W
0:4
1
0
M-T illegal SOP.
0: Disables the interrupt.
1: Enables the interrupt.
MT_IEOP_EN
R/W
0:5
1
0
M-T illegal EOP.
0: Disables the interrupt.
1: Enables the interrupt.
TM_PKTCD_EN
R/W
0:6
1
0
T-M packet cut down.
0: Disables the interrupt.
1: Enables the interrupt.
MT_PKTCD_EN
R/W
0:7
1
0
M-T packet cut down.
0: Disables the interrupt.
1: Enables the interrupt.
T_LOCKUN_EN
R/W
1:0
1
0
Tributary SPI4 ingress locker unavailable.
0: Disables the interrupt.
1: Enables the interrupt.
M_LOCKUN_EN
R/W
1:1
1
0
Main SPI4 ingress locker unavailable.
0: Disables the interrupt.
1: Enables the interrupt.
T_DCLKLOS_EN
R/W
1:2
1
0
Tributary ingress data clock lost.
0: Disables the interrupt.
1: Enables the interrupt.
T_SCLKLOS_EN
R/W
1:3
1
0
Tributary egress status clock lost.
0: Disables the interrupt.
1: Enables the interrupt.
M_DCLKLOS_EN
R/W
1:4
1
0
Main ingress data clock lost.
0: Disables the interrupt.
1: Enables the interrupt.
M_SCLKLOS_EN
R/W
1:5
1
0
Main egress status clock lost.
0: Disables the interrupt.
1: Enables the interrupt.
T_DIP2_EN
R/W
1:6
1
0
Tributary SPI4 DIP-2.
0: Disables the interrupt.
1: Enables the interrupt.
Table 140 PMON Event Interrupt Enable Register (Block Base=0x0F00, Register Offset=0x01)
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