參數(shù)資料
型號: IDT88K8483BRI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/162頁
文件大小: 0K
描述: IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88K8483BRI
102 of 162
October 20, 2006
IDT IDT88K8483
Secondary Interrupt COMMON Indication Register
Field
Read /
Write
Bits Length Reset
State
Description
TIMEBASE
R/W
0:0
1
0
This field indicates an event captured in the timebase.
Read 0: No event is generated.
Read 1: An event is generated by a timebase trigger.
Write 1: Clear the field.
INDIRECT_ACC R/W
0:1
1
0
This field indicates an event captured in the indirect access.
Read 0: No event is generated.
Read 1: An event is generated due to an invalid indirect access sequence.
Write 1: Clear the field.
I_FIFO_READY
R/W
0:2
1
This field indicates when the embedded processor is ready to accept data through the
I_FIFO
Read 0: I_FIFO not ready to accept data.
Read 1: I_FIFO ready to accept data.
Write 1: Resets the field.
I_FIFO_OFLOW R/W
0:3
1
0
This field indicates if the mailbox I_FIFO is oveflowed.
Read 0: No overflow in mailbox I_FIFO.
Read 1: Overflow in mailbox I_FIFO. An attempt to write more than 32 bytes generates
this interrupt.
Write 1: Clears this field.
O_FIFO_MSG
R/W
0:4
1
0
This field indicates when the embedded processor has data in its mailbox O_FIFO
Read 0: No data in present in O_FIFO.
Read 1: Data is present in O_FIFO.
Write 1: Resets the bit.
SOC
R/W
0:5
1
0
SOC trigger
10ms
R/W
0:6
1
0
This field generates a 10ms timer event based on the 1ms timer.
Read 0: 10ms timer event is not generated.
Read 1: 10ms timer event is generated.
Write 1: Resets the field.
Table 50 Interrupt secondary COMMON indication register (Register Offset=0xe)
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