參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 1/162頁
文件大小： 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標準包裝： 24
系列： *
其它名稱： 88K8483BRI
1 of 162
October 20, 2006
2006 Integrated Device Technology, Inc.
DSC 6214/-
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Description
The IDT88K8483 is a 3-port SPI-4 Exchange device. The IDT SPI-4
Exchange devices build on IDT’s proven SPI-4 implementation and
packet fragment processor (PFP) design. The IDT88K8483 suits appli-
cations with slow backpressure response and other advanced
networking applications when there is the need for duplicate ports to re-
route data multiple times through the packet-exchange and temporary
storage for complete in-flight packets.
The data on each SPI-4 interface logical port (LP) are mapped to a
logical identifier (LID). A data flow between logical port addresses on the
various interfaces is accomplished using LID maps that can be dynami-
cally reconfigured. The device enables the connection of two SPI-4
devices to a network processor having one or more SPI-4 interfaces. Up
to 18Mbit of additional buffer memory can be provided using the QDRII
interface. Alternatively, the HSTL I/O may be used to provide a generic
packet interface to a FPGA. The device supports a maximum of 128
logical ports.
Applications
– Ethernet transport
– SONET / SDH packet transport line cards
– Broadband aggregation
– Multi-service switches
– IP services equipment
– Security firewalls
Features
◆
Functionality
– Multiplexes logical ports (LPs) from SPI-4A and SPI-4B to SPI-
4M
– Optionally converts between interleaved packet transfers and
whole packet transfers per logical port
– Data redirection per LP between SPI-4A, SPI-4B and 10G
FPGA
– Per LP configurable memory allocation
– Per LP memory expansion via QDR-II SRAM interface
– 3 separate clock generators allowing fully flexible, fully inte-
grated clock derivations and generation
◆
Standard Interfaces
– Two OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range, 64
concurrently active LPs per interface
– One OIF SPI-4 phase 2: 80 - 450 MHz, 256 address range,
128 concurrently active LPs
– SPI-4 FIFO status channel options:
– LVDS full-rate, LVDS quarter-rate, LVTTL quarter-rate
– SPI-4 compatible with Network Processor Streaming Interface
(NPSI NPE-Framer mode of operation)
– HSTL Interface with selectable operating mode
160 - 200 MHz DDR packet interface, 64 concurrently active
LPs; or
QDR-II memory interface: 160 - 200MHz HSTL
– Serial or parallel microprocessor interface for control and
monitoring
– IEEE 1491.1 JTAG
Block Diagram
Figure 1 IDT88K8483 Block Diagram
SPI-4A
64 Logical
QDR-II 10Gbps
Packet Fragment
Processor A-TM (PFP)
Memory int.
10Gbps FPGA
Packet Int.
Ports
SPI-4B
64 Logical
Ports
Packet Fragment
Processor A-MT (PFP)
Packet Fragment
Processor B-TM (PFP)
Packet Fragment
Processor B-MT (PFP)
SPI-4M
128 Logical
Ports
Auxiliary
10Gbps
Interface
Tributary
SPI-4s
Main
SPI-4
Serial / 8bit
MicroprocessorInterface
Micro.
Int.
JTAG Interface
JTAG Int.
IDT88K8483
SPI-4 Exchange
Document Issue 1.0
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