參數(shù)資料
型號： IDT88K8483BRI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 10/162頁
文件大?。?/td> 0K
描述： IC SPI-4 EXCHANGE 3PORT 672-BGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88K8483BRI
107 of 162
October 20, 2006
IDT IDT88K8483
SPI-4 Ingress Training Parameter Register
SPI-4 Ingress Calendar 0 Configuration Register.
Field
Read /
Write
Bits
Length Reset
State
Description
FIFO_MAX_T
R/W
0:0-2:7
24
0
The SPI-4 ingress FIFO_MAX_T field is the maximum time interval between
scheduling of training sequences on the FIFO status path interface. The units are in
28 SPI-4 data cycles.
ALPHA_FIFO
R/W
3:0-3:7
8
0
The SPI-4 ingress ALPHA_FIFO field is the number of repetitions of the status
training sequence that must be scheduled every FIFO_MAX_T cycles. The value
for alpha used is actually one more than the ALPHA_FIFO value programmed into
the ALPHA_FIFO field.
Note: The purpose of the FIFO status path training sequence is for the deskew of bit arrival times on the FIFO status and control lines.
Table 59
SPI-4 Ingress Training Parameter Register (Block base=0x0300, Register Offset=0x02)
Field
Read /
Write
Bits
Length Reset
State
Description
I_CAL_M
R/W
0:0-0:7
8
0x01
The I_CAL_M value programmed defines the number of times the calendar 0
sequence is repeated before a DIP-2 parity and “1 1” framing words are inserted1.
The actual CALENDAR_M3 value used is one more than the value programmed
into the I_CAL_M field.
I_CAL_LEN
R/W
1:0-1:6
7
0x7
Indicates the length of the ingress calendar 02.The actual calendar length
CALENDAR_LEN3 is I_CAL_LEN+1.
In LVTTL mode, the I_CAL_LEN can be programmed with any value.
In LVDS mode, the I_CAL_LEN should be programmed with 4n-1, where n is an
integer.
Note:
1If the I_CSW_EN bit in SPI4 Ingress Calendar Switch Control Register (p. 109) is set to 1,then the I_CAL_M value defines the number of times the
calendar sequence is repeated before a DIP2 parity,’1 1’ framing word and calendar selection word are inserted.
2The calendar length CALENDAR_M must be at least as large as the number of active SPI-4 ingress LPs. CALENDAR_M must match the number of entries in
3CALENDAR_LEN and CALENDAR_M are described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1).
Table 60
SPI-4 Ingress Calendar 0 Configuration Register (Block Base=0x0300, Register Offset=0x03)
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