- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1916 > DS33ZH11+ (Maxim Integrated Products)IC MAPPER ETHERNET 100CSBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS33ZH11+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 95/172頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MAPPER ETHERNET 100CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 7 |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 接口： | 串行 |
| 電源電壓： | 1.8V，2.5V，3.3V |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 托盤(pán) |
| 安裝類(lèi)型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)當(dāng)前第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)
DS33Z11 Ethernet Mapper
29 of 172
8 FUNCTIONAL DESCRIPTION
The DS33Z11 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN
Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a
10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86(LAPS) Mapper,
SDRAM interface, control ports, and Bit Error Rate Tester (BERT).
The Ethernet Packet interface supports MII and RMII interfaces allowing DSZ33Z11 to connect to commercially
available Ethernet PHY and MAC devices. The Ethernet interface can be configured for 10 Mbps or 100 Mbps
service, in DTE and DCE configurations. The DS33Z11 MAC interface rejects frames with bad FCS and short
frames (less than 64 bytes).
Ethernet frames are queued and stored in external 32-bit SDRAM. The DS33Z11 SDRAM controller enables
connection to a 128Mbit SDRAM without external glue logic, at clock frequencies up to 100 MHz. The SDRAM is
used for both the Transmit and Receive Data Queues. The Receive Queue stores data to be sent from the Packet
interface to the WAN interface. The Transmit Queue stores data to be sent from the WAN interface to the Packet
interface. The external SDRAM can accommodate up to 8192 frames with a maximum frame size of 2016 bytes.
The sizing of the queues can be adjusted by software. The user can also program high and low watermarks for
each queue that can be used for automatic or manual flow control. The packet data stored in the SDRAM is
encapsulated in HDLC or X.86 (LAPS) to be transmitted over the WAN interface. The device also provides the
capability for bit and packet scrambling.
The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets over the
Ethernet port. The WAN physical interface supports serial data streams up to 52 Mbps. The WAN serial port can
operate with a gapped clock, and can be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier
transceiver for transmission to the WAN. The WAN interface can be connected to the Dallas
Semiconductor/Maxim T1/E1/J1 framers, LIUs, and SCTs. The WAN interface can also be connected to the
Dallas Semiconductor/Maxim T3/E3/STS-1 framers, LIUs, and SCTs to provide T3, E3, and STS1 connectivity.
The DS33Z11 can be configured through an 8-bit microprocessor interface port. A serial EEPROM (SPI) interface
and hardware mode are also included for applications without a host microprocessor. Operation without an
external host simplifies and reduces the cost of typical applications such as connectivity to T1/T3 and E1/E3 front
ends. The DS33Z11 also provides two on-board clock dividers for the System Clock input and Reference Clock
Input for the 802.3 interfaces, further reducing the need for ancillary devices.
8.1 Processor Interface
Microprocessor control of the DS33Z11 is accomplished through the 20 interface pins of the microprocessor port.
The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the two MODEC[1:0]
pins. When MODEC[1:0] = 00 and HWMODE = 0, bus timing is in Intel mode, as shown in Figure 11-9 and
Figure 11-10. When MODEC[1:0] = 01 and HWMODE = 0, bus timing is in Motorola mode, as shown in Figure
11-11 and Figure 11-12. The address space is mapped through the use of 8 address lines, A0-A7. Multiplexed
Mode is not supported on the processor interface.
The Chip Select (
CS) pin must be brought to a logic low level to gain read and write access to the microprocessor
port. With Intel timing selected, the Read (
RD) and Write (WR) pins are used to indicate read and write operations
and latch data through the interface. With Motorola timing selected, the Read-Write (R
W) pin is used to indicate
read and write operations while the Data Strobe (
DS) pin is used to latch data through the interface.
The interrupt output pin (
INT) is an open-drain output that will assert a logic-low level upon a number of software
maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The register
map is shown in Table 9-1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS34C87TN/NOPB | IC LINE DRIVER QUAD CMOS 16-DIP |
| DS34LV87TMX/NOPB | IC LINE DVR QUAD CMOS DIF 16SOIC |
| DS34S132GN+ | IC TDM OVER PACKET 676-BGA |
| DS34T102GN+ | IC TDM OVER PACKET 484TEBGA |
| DS3501U+H | IC POT NV 128POS HV 10-USOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS33ZH11+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 10/100 ENETXPORT HMODE MAP IND RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS34 | 制造商:LUMILEDS 制造商全稱(chēng):LUMILEDS 功能描述:power light source Luxeon V Emitter |
| DS-3400D UK | 制造商:TRUST 功能描述:DESKTOP WIRELESS OPTICAL TRUST |
| DS3404FP000 | 制造商:Thomas & Betts 功能描述:30A,PLG,3P4W,MG,404,3P480V |
| DS3404FP000/JG63 | 制造商:Thomas & Betts 功能描述:30A,CON,3P4W,MG,404,3P480V,JG63,SC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。