參數資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數： 101/172頁
文件大小： 0K
描述： IC MAPPER ETHERNET 100CSBGA
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 7
應用： 數據傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應商設備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
34 of 172
8.4 Resets and Low Power Modes
The external
RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset
signal resets the status and control registers on the chip (except the GL.CR1. RST bit) to their default values and
resets all the other flops to their reset values. The processor bus output signals are also placed in high-
impedance mode when the
RST pin is active (low). The global reset bit (GL.CR1. RST) stays set after a one is
written to it, but is reset to zero when the external
RST pin is active or when a zero is written to it. Allow 5
milliseconds after initiating a reset condition for the reset operation to complete.
The Serial Interface reset bit in LI.RSTPD resets all the status and control registers on the Serial interface to their
default values, except for the LI.RSTPD.RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
If DS33Z11 is configured to use an external EEPROM, the DS33Z11 will provide the startup sequence to read the
device settings upon the rising edge of the external
RST pin. When using the external EEPROM the device is
configured within 5 ms. This is dependent on an EEPROM clock of 8.33 MHz. The functional timing is provided by
Table 8-2 Reset Functions
RESET FUNCTION
LOCATION
COMMENTS
Hardware Device Reset
RST Pin
Transition from a logic 0 to a logic 1
resets the device.
Hardware JTAG Reset
JTRST Pin
Resets the JTAG test port.
Global Software Reset
Writing to this bit resets the device.
Serial interface Reset
Writing to this bit resets the Serial
Interface.
Queue Pointer Reset
Writing to this bit resets the Queue
Pointers
There are several features in the DS33Z11 to reduce power consumption. The reset bit in the LI.RSTPD register
minimizes power usage in the Serial Interface. Additionally, the
RST pin or GL.CR1.RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization
and configuration. For the lowest possible standby current, clocks may be externally gated.
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