參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 88/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
22 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
D6
C5
—
IOZ
Data Bit 6: Bidirectional data bit 6 of the microprocessor
interface. Not driven when
CS = 1 or RST = 0.
D7
C6
—
IOZ
Data Bit 7: Bidirectional data bit 7 of the microprocessor
interface. Most Significant Bit.
CS = 1 or RST = 0.
SPI_CS
B8
B5
O
Active-Low SPI Chip Select: Provides the chip select to
the external EEPROM, when the SPI port is in master
mode.
CKPHA
F6
—
I
SPI Clock Phase: MISO is sampled on the falling edge
when CKPHA is set high, and on the rising edge when set
low.
MOSI is updated on the rising edge when CKPHA is set
high, and on the falling edge when set low.
CS
C1
—
I
Active-Low Chip Select: This pin must be taken low for
read/write operations. When
CS is high, the RD/DS and
WR signals are ignored.
RD/DS
E1
—
I
Active-Low Read-Data Strobe (Intel Mode): The
DS33Z11 drives the data bus (D0-D7) with the contents of
the addressed register while
RD and CS are both low.
Active-Low Data Strobe (Motorola Mode): Used to latch
data through the microprocessor interface.
DS must be
low during read and write operations.
WR/RW
E2
—
I
Active-Low Write (Intel Mode): The DS33Z11 captures
the contents of the data bus (D0-D7) on the rising edge of
WR and writes them to the addressed register location.
CS must be held low during write operations.
Read Write (Motorola Mode): Used to indicate read or
write operation. R
W must be set high for a register read
cycle and low for a register write cycle.
INT
F3
—
OZ
Active-Low Interrupt Output: Outputs a logic zero when
an unmasked interrupt event is detected.
INT is
deasserted when all interrupts have been acknowledged
and serviced. Inactive state is programmable in register
RST
D8
C1
I
Active-Low Reset: An active low signal on this pin resets
the internal registers and logic. This pin should remain low
until power, SYSCLKI, RX_CLK, and TX_CLK are stable,
then set high for normal operation. In DCE and RMII
modes, the REF_CLK input must also have a stable clock
input before setting RST high for normal operation. This
input requires a clean edge with a rise time of 25ns or less
to properly reset the device.
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