參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 76/172頁
文件大小： 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 7
應用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應商設備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
167 of 172
Table 12-1 Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE:PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
12.2.1 SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal
operation of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data
into the boundary scan register via JTDI using the Shift-DR state.
12.2.2 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
12.2.3 EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR will sample
all digital inputs into the boundary scan register.
12.2.4 CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the
bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
12.2.5 HIGHZ
All digital outputs of the device are placed in a high-impedance state. The BYPASS register is connected between
JTDI and JTDO.
12.2.6 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code is loaded into the identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The
ID code will always have a ‘1’ in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number
and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
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