參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 84/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
19 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
TX_EN
E10
B6
O
Transmit Enable (MII): This pin is asserted high when
data TXD [3:0] is being provided by the DS33Z11. The
signal is deasserted prior to the first nibble of the next
frame. This signal is synchronous with the rising edge
TX_CLK. It is asserted with the first bit of the preamble.
Transmit Enable (RMII): When this signal is asserted, the
data on TXD [1:0] is valid. This signal is synchronous to
the REF_CLK.
TXD[0]
B9
A8
TXD[1]
C9
B7
TXD[2]
D9
B8
TXD[3]
E9
A9
O
Transmit Data 0 through 3(MII): TXD [3:0] is presented
synchronously with the rising edge of TX_CLK. TXD [0] is
the least significant bit of the data. When TX_EN is low
the data on TXD should be ignored.
Transmit Data 0 through 1(RMII): Two bits of data TXD
[1:0] presented synchronously with the rising edge of
REF_CLK.
RX_CLK
A10
B10
IO
Receive Clock (MII): Timing reference for RX_DV,
RX_ERR and RXD[3:0], which are clocked on the rising
edge. RX_CLK frequency is 25 MHz for 100 Mbps
operation and 2.5 MHz for 10 Mbps operation. In DTE
mode, this is a clock input provided by the PHY. In DCE
mode, this is an output derived from REF_CLK providing
2.5 MHz (10 Mbps operation) or 25 MHz (100 Mbps
operation).
RXD[0]
B11
D9
RXD[1]
C11
D10
RXD[2]
D11
C9
RXD[3]
A11
C10
I
Receive Data 0 through 3(MII): Four bits of received
data, sampled synchronously with the rising edge of
RX_CLK. For every clock cycle, the PHY transfers 4 bits
to the DS33Z11. RXD[0] is the least significant bit of the
data. Data is not considered valid when RX_DV is low.
Receive Data 0 through 1(RMII): Two bits of received
data, sampled synchronously with REF_CLK with 100
Mbps Mode. Accepted when CRS_DV is asserted. When
configured for 10 Mbps Mode, the data is sampled once
every 10 clock periods.
RX_DV
D10
A10
I
Receive Data Valid (MII): This active high signal indicates
valid data from the PHY. The data RXD is ignored if
RX_DV is not asserted high.
RX_CRS/
CRS_DV
C8
I
Receive Carrier Sense (MII): Should be asserted (high)
when data from the PHY (RXD[3:0) is valid. For each
clock pulse 4 bits arrive from the PHY. Bit 0 is the least
significant bit. In DCE mode, connect to VDD.
Carrier Sense/Receive Data Valid (RMII): This signal is
asserted (high) when data is valid from the PHY. For each
clock pulse 2 bits arrive from the PHY. In DCE mode, this
signal must be grounded.
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