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參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 89/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 7
應用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應商設備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
23 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
HWMODE
D5
A3
I
Hardware Mode: Connect to VDD to place the device in
Hardware Mode. MODEC[1:0] determines the default
hardware setting to be used. This pin must be held low for
control by a microprocessor or an external EEPROM.
MODEC[0]
D6
—
MODEC[1]
D7
A4
I
Mode Control:
Software Mode Options (HWMODE = 0)
00 = Read/Write Strobe Used (Intel Mode)
01 = Data Strobe Used (Motorola Mode)
10 –SPI Master Mode (External EEPROM)
11- Reserved. Do not use.
Hardware Mode Options (HWMODE = 1)
00 = Default Hardware Mode. See Table 8-8.
01 = Reserved. Do not use.
10 = Hardware Mode for T3/E3 rates. See Table 8-8.
11 = Reserved. Do not use.
Note that in the 100-pin CSBGA (DS33ZH11) package,
only MODEC[1] is available to the user. MODEC[0] is
internally connected to VSS.
DCEDTES
A13
—
I
DCE or DTE Selection: The user must set this pin high
for DCE Mode selection or low for DTE Mode. This input
affects operation in both software and hardware mode. In
DCE Mode, the DS33Z11 MAC port can be directly
connected to another MAC. In DCE Mode, the Transmit
clock (TX_CLK) and Receive clock (RX_CLK) are output
by the DS33Z11.
Note that there is no software bit selection of DCEDTES.
Note that DCE Mode is only relevant when the MAC
interface is in MII mode.
RMIIMIIS
C4
—
I
RMII or MII Selection: Set high to configure the MAC for
RMII interfacing. Set low for MII interfacing. This pin is tied
low in the 100 pin CSBGA (DS33ZH11) package option.
FULLDS
A9
—
I
Full Duplex Selection (Hardware Mode): When in
Hardware Mode, this pin must be set to 1 for proper
operation (Full Duplex Mode). In software mode, this pin
has no effect and duplex selection is controlled in the
SU.GCR register. This pin is tied high in the 100 pin
CSBGA (DS33ZH11) package option.
H10S
B10
—
I
100Mb/10Mb (Hardware Mode): When in Hardware
Mode, this pin selects the packet PHY data rate. Set high
for 100 Mbps. Set low for the MII/RMII interface to run at
10 Mbps. In the software mode this pin has no effect and
the rate selection is controlled in the SU.GCR register.
Note that in the 100-pin CSBGA (DS33ZH11) package,
this pin is internally tied to VDD.
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