參數(shù)資料
型號: DS33ZH11+
廠商: Maxim Integrated Products
文件頁數(shù): 91/172頁
文件大小: 0K
描述: IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 7
應(yīng)用: 數(shù)據(jù)傳輸
接口: 串行
電源電壓: 1.8V,2.5V,3.3V
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 托盤
安裝類型: 表面貼裝
DS33Z11 Ethernet Mapper
25 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
SDA[6]
L9
G5
SDA[7]
L5
G4
SDA[8]
M5
F8
SDA[9]
M7
F5
SDA[10]
M8
H5
SDA[11]
N8
K4
DS33Z11. No user programming for SDRAM buffering is
required.
SBA[0]
M6
F7
SBA[1]
N7
J4
I
SDRAM Bank Select: These two bits select 1 of 4 banks
for the read/write/precharge operations.
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
SRAS
K6
K3
O
Active-Low SDRAM Row Address Strobe: Used to latch
the row address on rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode
Register Write.
SCAS
H4
F4
O
Active-Low SDRAM Column Address Strobe: Used to
latch the column address on the rising edge of SDCLKO.
It is used with commands for Bank Activate, Precharge,
and Mode Register Write.
SWE
M4
G3
O
Active-Low SDRAM Write Enable: This output enables
write operation and auto precharge.
SDMASK[0]
N6
F3
SDMASK[1]
G4
E3
SDMASK[2]
M10
J6
SDMASK[3]
M9
C5
O
SDRAM Mask 0 through 3: When high, a write is done
for that byte. The least significant byte is SDATA7 to
SDATA0. The most significant byte is SDATA31 to
SDATA24.
SDCLKO
N5
J3
O
(4mA)
SDRAM CLK Out: System clock output to the SDRAM.
This clock is a buffered version of SYSCLKI.
SYSCLKI
G13
K10
I
System Clock In: 100MHz System Clock input to the
DS33Z11, used for internal operation. This clock is
buffered and provided at SDCLKO for the SDRAM
interface. The DS33Z11 also provides a divided version
output at the REF_CLKO pin. A clock supply with ±100
ppm frequency accuracy is suggested.
SDCS
L6
H3
O
Active-Low SDRAM Chip Select: This output enables
SDRAM access.
QUEUE STATUS
QOVF
C7
O
Queue Overflow: This pin goes high when the transmit or
receive queue has overflowed. This pin goes low when the
high watermark is reached again. This pin functions in
both software and hardware mode.
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