CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION OF 128 KB OR LESS AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS)
User’s Manual U16890EJ1V0UD
771
(b) Write cycle (CLKOUT asynchronous): In separate bus mode
(T
A
=
40 to +85
°
C, V
DD
= EV
DD
= AV
REF0
= 4.0 to 5.5 V, 4.0 V
≤
BV
DD
≤
V
DD
, 4.0 V
≤
AV
REF1
≤
V
DD
, V
SS
= EV
SS
=
BV
SS
= AV
SS
= 0 V, C
L
= 50 pF) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to WRm
↓
)
t
SAWR
<52>
(1 + t
ASW
+ t
AHW
)T
60
ns
Address hold time (from WRm
↑
)
t
HAWR
<53>
0.5T
10
ns
WRm low-level width
t
WWRL
<54>
(0.5
+
n)T
10
ns
Data output time from WRm
↓
t
DOSDW
<55>
5
ns
Data setup time (to WRm
↑
)
t
SOSDW
<56>
(0.5
+
n)T
20
ns
Data hold time (from WRm
↑
)
t
HOSDW
<57>
0.5T
20
ns
Data setup time (to address)
t
SAOD
<58>
(1 + t
ASW
+ t
AHW
)T
30
ns
t
SWRWT1
<59>
30
ns
WAIT setup time (to WRm
↓
)
t
SWRWT2
<60>
nT
30
ns
t
HWRWT1
<61>
0
ns
WAIT hold time (from WRm
↓
)
t
HWRWT2
<62>
nT
ns
t
SAWT1
<63>
(1 + t
ASW
+ t
AHW
)T
45
ns
WAIT setup time (to address)
t
SAWT2
<64>
(1 + n + t
ASW
+ t
AHW
)T
45
ns
t
HAWT1
<65>
(n + t
ASW
+ t
AHW
)T
ns
WAIT hold time (from address)
t
HAWT2
<66>
(1
+
n + t
ASW
+ t
AHW
)T
ns
Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k
= 0, 1).
1/
f
CPU
< 60 ns
Set an address setup wait (ASWk bit = 1).
Remarks
1.
m = 0, 1
2.
t
ASW
: Number of address setup wait clocks
t
AHW
: Number of address hold wait clocks
3.
T = 1/f
CPU
(f
CPU
: CPU operating clock frequency)
4.
n: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
5.
The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.