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CHAPTER 27 FLASH MEMORY (TWO POWER)
User’s Manual U16890EJ1V0UD
683
Table 27-1. Wiring Between
μ
PD70F3214 and 70F3214Y, and PG-FP4
Pin Configuration of Flash Programmer (PG-FP4)
With CSI00-HS
With CSI00
With UART0
Pin No.
Pin No.
Pin No.
Signal Name
I/O
Pin Function
Pin Name on
FA Board
Pin Name
GC
GF
Pin Name
GC
GF
Pin Name
GC
GF
SI/R
X
D
Input
Receive signal
SI
P41/SO00
23
25
P41/SO00
23
25
P30/TXD0
25
27
SO/T
X
D
Output
Transmit signal
SO
P40/SI00
22
24
P40/SI00
22
24
P31/RXD0
26
28
SCK
Output
Transfer clock
SCK
P42/SCK00 24
26
P42/SCK00 24
26
Not needed Not needed
X1
X1
12
14
X1
12
14
X1
12
14
CLK
Output
Clock to V850ES/KG1
X2
X2
Note 1
13
15
X2
Note 1
13
15
X2
Note 1
13
15
/RESET
Output
Reset signal
/RESET
RESET
14
16
RESET
14
16
RESET
14
16
VPP
Output
Write voltage
VPP
V
PP
8
10
V
PP
8
10
V
PP
8
10
HS
Input
Handshake signal for
CSI00 + HS
communication
RESERVE/
HS
PCS1/
CS1
Note 2
60
62
Not needed Not needed Not needed Not needed
V
DD
9
11
V
DD
9
11
V
DD
9
11
BV
DD
70
72
BV
DD
70
72
BV
DD
70
72
EV
DD
34
36
EV
DD
34
36
EV
DD
34
36
AV
REF0
1
3
AV
REF0
1
3
AV
REF0
1
3
VDD
I/O
V
DD
voltage
generation/voltage
monitor
VDD
AV
REF1
5
7
AV
REF1
5
7
AV
REF1
5
7
V
SS
11
13
V
SS
11
13
V
SS
11
13
AV
SS
2
4
AV
SS
2
4
AV
SS
2
4
BV
SS
69
71
BV
SS
69
71
BV
SS
69
71
GND
Ground
GND
EV
SS
33
35
EV
SS
33
35
EV
SS
33
35
Notes 1.
When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its
inverse signal to X2.
2.
The pin differs when it is used in a single-power flash memory.
Cautions 1. Be sure to connect the REGC pin in either of the following ways.
Connect to GND via a 10
μ
F capacitor
Directly connect to V
DD
2. When connecting the REGC pin to GND via a 10
μ
F capacitor, the clock cannot be supplied from
the CLK pin of the flash programmer.
Supply the clock by creating an oscillator on the board.
Remark
GC: 100-pin plastic LQFP (fine pitch) (14
×
14)
GF: 100-pin plastic QFP (14
×
20)