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CHAPTER 1 INTRODUCTION
User’s Manual U16890EJ1V0UD
36
1.6 Function Block Configuration
(1) Internal block diagram
NMI
TO00 to TO03
TI000, TI001, TI010, TI011,
TI020, TI021, TI030, TI031
SO00, SO01
SI00, SI01
SCK00, SCK01
INTP0 to INTP6
INTC
16-bit
timer/event
counter 0: 4 ch
TOP00, TOP01
Note 3
TIP00, TIP01
Note 3
16-bit timer/
event counter
P
Note 3
: 1 ch
TO50, TO51
TI50, TI51
8-bit
timer/event
counter 5: 2 ch
TOH0, TOH1
TXD0, TXD1
RXD0, RXD1
ASCK0
RTP00 to RTP05
KR0 to KR7
UART
: 2 ch
CSIA
: 2 ch
RTO: 1 ch
SDA0
Note 4
SCL0
Note 4
I
2
C
Note 4
:
1 ch
Watchdog
timer: 2 ch
Key interrupt
function
Regulator
Watch timer
Note 1
Note 2
RAM
ROM
PC
Genregisters
32 bits
×
32
Multiplier
16
×
16
→
32
ALU
System
register
32-bit barrel
shifter
CPU
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
CS0, CS1
A0 to A21
AD0 to AD15
Port
A/D
converter
D/A
converter
P
P
P
P
P
P
P
P
P
P
P
A
A
R
R
A
R
A
S
A
V
DD
V
PP
Note 5
/IC
Note 5
/FLMD0
Note 5
FLMD1
Note 5
BV
DD
BV
SS
EV
DD
EV
SS
V
SS
Instruction
queue
BCU
SOA0, SOA1
SIA0, SIA1
SCKA0, SCKA1
CSI0: 2 ch
8-bit timer H:
2 ch
ROM
correction
CG
PLL
CLKOUT
X1
X2
XT1
XT2
RESET
Notes 1.
μ
PD703212, 703212Y:
μ
PD703213, 703213Y:
μ
PD703214, 703214Y:
μ
PD703215, 703215Y:
μ
PD70F3214, 70F3214Y, 70F3214H, 70F3214HY: 128 KB (flash memory)
μ
PD70F3215H, 70F3215HY:
2.
μ
PD703212, 703212Y, 703213, 703213Y:
μ
PD703214, 703214Y, 70F3214, 70F3214Y, 70F3214H, 70F3214HY: 6 KB
μ
PD703215, 703215Y, 70F3215H, 70F3215HY:
3.
Only in the
μ
PD703215, 703215Y, 70F3215H, 70F3215HY
4.
Only in the
μ
PD703212Y, 703213Y, 703214Y, 703215Y, 70F3214Y, 70F3214HY, 70F3215HY
5.
IC:
μ
PD703212, 703212Y, 703213, 703213Y, 703214, 703214Y, 703215, 703215Y
V
PP
:
μ
PD70F3214, 70F3214Y
FLMD0, FLMD1:
μ
PD70F3214H, 70F3214HY, 70F3215H, 70F3215HY
64 KB (mask ROM)
96 KB (mask ROM)
128 KB (mask ROM)
256 KB (mask ROM)
256 KB (flash memory)
4 KB
16 KB