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PEB 3445 E
Functional Description
Data Sheet
40
2001-06-29
4.4
M12 Multiplexer/Demultiplexer and DS2 framer
The M12 multiplexer and the DS2 framer can be operated in two modes:
M12 multiplex format according to ANSI T1.107
ITU-T G.747 format
4.4.1
The framing structure of the M12 signal is shown in
Table 1
. A DS2 multiframe consists
of four subframes. Each subframe combines 6 blocks with 49 bits each. The first bit of
each block contains an overhead (OH) bit and 48 information bits. The 48 information
bits are formed by bit-by-bit interleaving of the four DS1 signals or a total of 12 bits from
each DS1 signal. The first bit is assigned to the 1
st
tributary DS1 signal, the second bit
is assigned to the 2
nd
tributary DS1 signal and so on.
M12 multiplex format
Table 1
M12 multiplex format
M
0
, M
1
M
0
and M
1
form the multiframe alignment signal. Each DS2 multiframe consists of three M-bits
and they are located in bit 0 of subframe one through three. The multiframe alignment signal is
’011’.
X
This bit is the fourth bit of the multiframe alignment signal and can be set to either ’0’ or ’1’. It is
accessible via an internal register.
F
0
, F
1
F
0
and F
1
form the frame alignment pattern. Each DS2 multiframe consists of eight F-bits, two
per subframe in block 3 and 6. F
0
and F
1
form the pattern ’01’. This pattern is repeated in every
subframe.
C
11
..C
43
The C-bits control the bit stuffing procedure of the multiplexed DS1 signals.
[48]
These bits represent a data block, which consists of 48 bits. [48] consists of four time slots of 12
bit and each time slot is assigned to one of four participating DS1 signals.
Subframe
Block 1 through 6 of a subframe
2
3
[48] C
11
[48]
F
0
[48] C
12
[48] C
13
[48]
[48] C
21
[48]
F
0
[48] C
22
[48] C
23
[48]
[48] C
31
[48]
F
0
[48] C
32
[48] C
33
[48]
[48] C
41
[48]
F
0
[48] C
42
[48] C
43
[48]
1
4
5
6
DS2-
Multiframe
1
2
3
4
M
0
M
1
M
1
X
F
1
F
1
F
1
F
1
[48]
[48]
[48]
[48]