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PEB 3445 E
Register Description
Data Sheet
109
2001-06-29
SR
Status Register Change
This bit indicates a change in DS3 or DS2 status. The status is shown is
register D3RINTC. The related port is indicated in bit field GN.
Group Number
This bit field indicates the port where a status change or loopback code
change occurred.
0..6
Status change of DS2 framer 0..6.
7
Status change of DS3 framer.
Receive Spare Data Link Buffer Full
This bit indicates that new DL bits have been received in register
D3RSDL. If enabled it is generated with every multiframe to synchronize
reading of register D3RSDL.
Transmit Spare Data Link Buffer Empty
This bit indicates that new DL bits shall be written to register D3TSDL. If
enabled it is generated with every multiframe to synchronize writing of
register D3RSDL.
Test Unit Status Change
This bit indicates a status change of the test unit. Subsequently the
status can be read in register D3RINTC.
1 Second
The ‘One Second’ interrupt is generated every second.
All Sent
The ’All Sent’ interrupt is generated, when the last bit of a frame to be
transmitted is completely sent out and XFF.XFIFO is empty.
Transmit Data Underrun
The ’Transmit Data Underrun’ interrupt is generated, when the transmit
FIFO of the corresponding channel runs out of data during transmission
of a frame. The protocol controller terminates the affected frame.
Transmit Pool Ready
The ’Transmit Pool Ready’ interrupt is generated, when a new data block
of up to 32 bytes can be written to transmit FIFO. ’Transmit Pool Ready’
is the fastest way to access the transmit FIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with shared
flag.
Receive Pool Full
This bit is set, when the receive threshold is reached and data has to be
read from the receive FIFO. The frame is not yet completely received.
GN
RDL
TDL
TU
1S
ALLS
XDU
XPR
RPF